Method and apparatus for limiting the output frequency of an...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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C713S501000, C713S503000

Reexamination Certificate

active

07472305

ABSTRACT:
Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the internal clock signal frequency and the reference clock input signal frequency with minimum and maximum calibration word signals, in order to determine if the reference clock input signal frequency is within a permitted range. If the reference clock input signal frequency is not within the permitted range, the apparatus sends a tamper alert to the chip or to a system, and the output clock signal frequency is not changed according to the reference clock input signal frequency, thereby protecting the chip from erroneous or tampered clock signal. The output clock signal is buffered from the reference clock input signal insuring that the output clock signal frequency is within the permitted range. The apparatus can operate without providing the reference input clock signal.

REFERENCES:
patent: 6259279 (2001-07-01), Galbraith et al.
patent: 6683502 (2004-01-01), Groen et al.
patent: 2005/0140571 (2005-06-01), Hara et al.

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