Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-11-13
2007-11-13
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S502000
Reexamination Certificate
active
11054279
ABSTRACT:
One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. The system then uses the clock signal to limit the maximum repetition rate of the asynchronous circuit so that only a predetermined number of asynchronous transactions may take place during each cycle of the clock signal.
REFERENCES:
patent: 4131854 (1978-12-01), Schollmeier
patent: 4353128 (1982-10-01), Cummiskey
patent: 6990550 (2006-01-01), Hesse et al.
patent: 2003/0201796 (2003-10-01), Ebergen et al.
Coates William S.
Drost Robert J.
Ebergen Jo C.
Jones Ian W.
Abbaszadeh Jaweed A
Lee Thomas
Park Vaughan & Fleming LLP
Sun Microsystems
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