Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1998-05-12
2000-12-26
Robertson, David L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
713324, 365222, G11C 700
Patent
active
061674842
ABSTRACT:
A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.
REFERENCES:
patent: 5875143 (1999-02-01), Ben-Zvi
Nitta et al., "SP23.5: A 1.6GB/s Data Rate 1Gb-Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture," ISSCC96/Session 23/DRAM/Paper SP23.5, pp. 376-377 & 477.
Yoo et al., "SP23.6: A 32-Bank 1Gb DRAM with 1GB/s Bandwidth," ISSCC96/Session 23/DRAM/Paper SP23.6, pp. 378-379 and 477.
Itoh et al., "Trends in Low-Power RAM Circuit Technologies," 1994 IEEE Symposium on Low Power Electronics, pp. 84-87.
"Literature Survey and Analysis of Low-Power Techniques for Memory and Microprocessors," Bower; Web site: http//infopad.eecs.berkeley.edu/.about.bhowers/project2.html.
"A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture," Nitta, et al; ISSCC96/Session 23/DRAM/Paper SP23.5.
"Trends in Low-Power RAM Circuit Technologies," Itoh, et al; Proceedings of the IEEE, vol. 83, No. 4, Apr. 1995.
"A 32-Bank 1Gb DRAM with 1GB/s Bandwidth," Yoo, et al.; ISSCC96/Session 23/DRAM/Paper SP 23.6.
Boyer John Mark
Bruce, Jr. William Clayton
Giles Grady Lawrence
Johnston Thomas K.
Pappert Bernard J.
Motorola Inc.
Robertson David L.
LandOfFree
Method and apparatus for leveraging history bits to optimize mem does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for leveraging history bits to optimize mem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for leveraging history bits to optimize mem will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1006539