Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-09-22
2004-05-04
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S112000, C327S185000, C327S225000, C327S437000, C326S068000, C326S083000
Reexamination Certificate
active
06731151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to methods and circuits for low power consuming high-voltage level shifting and related circuitry.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Many integrated circuits, such as display drivers, require a combination of high-voltage driving capability (an output voltage swing up to 100V or more) and a digital control using standard 5V CMOS logic. Hence, complex level-shifting circuits are needed to convert the 5V control signals into the desired high-voltage output waveforms. Moreover, in many of those applications, the system is battery-powered and very severe constraints are put on the power consumption of the level-shifters. An application where both high-voltage driving capability and extremely low power consumption are required is the design of driver chips for cholesteric texture LCDs as discussed by J. W. Doane, D. K. Yang and Z. Yaniv in their paper, “Front-lit Flat Panel Display From Polymer Stabilized Cholsteric Textures”, in the proceedings of the 12
th
International Display Research Conference (Japan 1992), p. 73. As discussed in the paper, quite high voltage levels (50V rms) are necessary to switch this kind of liquid crystal from one stable state to another. However, its inherent memory function (images remain unchanged on the screen without the need for continuous refreshing) is a major advantage compared to other types of liquid crystals, as it allows the implementation of certain display systems with very low image frame rates and a high degree of power efficiency. Consequently, these cholesteric texture LCDs are ideal components for use in battery-operated display systems with slowly or sporadically varying images. The cholesteric texture LCD's do, however, require the development of the generation of the required waveforms on the display rows and columns, and high-voltage driver circuits with very low power dissipation.
In most high-voltage CMOS technologies five different kinds of n- and p-type MOS transistors, such as shown in
FIGS. 1A-1E
, are used. The devices shown in FIG.
1
(
a
) and FIG.
1
(
b
) are standard non-floating NMOS and floating PMOS transistors for normal 5V operation (used in the CMOS control logic). The PMOS device shown in FIG.
1
(
c
) can float up to a high voltage with respect to the substrate potential. However, in the PMOS device of FIG.
1
(
c
) V
GS
(the voltage between the gate and the source) and V
DS
(the voltage between the drain and the source) are limited to 5V, and hence this transistor is ideally suited for controlling the gate electrode of the PDMOS transistor in the output stage. It also serves very well as an active load in a voltage mirror. The NDMOS and floating PDMOS MOSFETs shown in FIG.
1
(
d
) and FIG.
1
(
e
) respectively have to withstand a high voltage between their source and drain electrodes (such as the ones in the output stage or the switching transistors in the voltage mirrors).
One basic version of a high-voltage level-shifter is the well-known circuit shown in FIG.
2
. This circuit exhibits a classic complementary output stage with independent control of the gate voltages of the NDMOS and PDMOS transistors
30
and
32
respectively. Standard 5V logic is used to control the NDMOS transistor
30
, while a voltage mirror made up of transistors
34
and
36
is required to apply the appropriate gate signal to the PDMOS transistor
32
. Unfortunately, the gate control of the PDMOS transistor
32
is not optimum, as is demonstrated by HSPICE-simulations represented by the graphs of FIG.
3
. These HSPICE-simulations are based on transistor model parameters from a high-voltage extension of a 0.7 &mgr;m CMOS technology. When the input data line shown at
38
in FIG.
3
(
b
) is switched from a logical “1” to “0”, the V
GS
of transistors
36
and
32
is not entirely discharged to 0V but to a value of approximately −1V, being the threshold voltage of the PMOS transistor
36
. Consequently, the PDMOS output transistor
32
, having a slightly different threshold voltage, is not driven 100% into cut-off operation, resulting in an output voltage of 0.5V instead of the ideal 0V value as shown at
40
in FIG.
3
(
c
). Moreover, the simultaneous conduction of both DMOS transistors
30
and
32
in the output stage represents a significant waste of energy.
The problem can be solved by discharging the V
GS
of the PDMOS output transistor
32
completely to 0V by means of a current mirror as illustrated in FIG.
4
. It should be noted that common components of
FIGS. 2 and 4
carry the same reference numbers. On the “1” to “0” transition of the input signal
40
, the constant current source
42
providing a current I
BIAS
and the current mirror transistors
44
and
46
ensure that the V
GS
of transistors
32
and
34
is pulled down to 0V as shown at
48
in FIG.
5
(
c
), resulting in a satisfactory logical “0” state at the driver output and avoiding the unnecessary power dissipation in the output DMOS transistors.
FIG. 5
shows the HSPICE-simulation results on this circuit. An alternative approach to the circuit of
FIG. 4
is the level-shifter proposed by M. Declercq and M. Schubert in their paper, “Circuit Intermédiaire Entre Un Circuit Logique à Basse Tension et un étage de Sortie à Haute Tension Réalises Dans Une Technolgie CMOS Standard”, also identified as patent 92 06030 at the Institut National de la Propriété Industrielle, Paris (France), where the current source
42
is no longer constant but controlled by the inverted input signal, resulting in a balanced circuit configuration. However, the level-shifter of FIG.
4
and all the variations described in the literature, have one major drawback: they show continuous power dissipation in the voltage mirrors for a logical “0” and/or a logical “1” at the data input. In the case of the simulation in FIG.
5
(
a
) for instance, it can be seen that a stationary 150 &mgr;A current is flowing through the drain termination of transistor
34
when a logical “1” bit is applied to the data input. This, of course, is unacceptable in battery-powered applications.
When considering cholesteric texture LCD drivers low-power high-voltage CMOS level-shifters cannot be used directly because they have a purely digital output (the output voltage is switched between 0V and V
HV
Supply voltage), while the cholesteric texture LCDs need waveforms which are far more complicated. Some of the driving schemes require three-, four- or even five-level logic, and others need analog multiplexers to select complex analog waveforms. Hence, for all those applications, an analog switch, capable of withstanding high voltages and exhibiting the same extremely low power dissipation as high-voltage level-shifters, is needed. One classic circuit for a high-voltage analog switch is shown in FIG.
6
. In this complementary analog switch, two diodes
50
and
52
have been included to avoid the unwanted conduction of the drain-bulk diodes in the DMOS transistors. To obtain the conducting “ON” state of the switch, the source-gate voltages of the DMOS devices should be V
GS,N
=V
GS,P
=OV is needed. Although the circuit is widely used in all kinds of applications, it has some important drawbacks: since the gate potential of the PDMOS transistor
54
has to be 5V lower than the V
HV
analog signal on input
56
to put the switch in the conducting “ON” state and since the gate potential of the NDMOS transistor
58
should exceed the V
HV
signal with 5V under the same circumstances, the voltage range of the control circuit (responsible for applying the appropriate signals to the gates of the 2 DMOS transistors) should be at least 10V in excess of the total V
HV
range. For the control of the NDMOS transistor
58
, a double voltage mirror is required. The first one shifts the 5V control input signals upwards towards an auxiliary supply voltage that is at least 5V higher than the highest V
HV
value, and then the second voltage mirror shifts these signals d
Buchel, Jr. Rudolph J.
Interuniversitar Micro-Elektronica Centrum (IMEC vzw)
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