Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-02-28
2004-09-21
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S201000
Reexamination Certificate
active
06795364
ABSTRACT:
FIELD OF THE INVENTION
The present invention is applicable to semiconductor memories, especially dynamic random access memory (DRAM). In particular, the present invention relates to a method and apparatus for controlling refresh operations in a semiconductor memory such that the data retention time in standby mode is made'significantly longer than the data retention time in a normal operating mode.
RELATED ART
Due to charge leakage, data stored in a DRAM cell must be refreshed periodically. The time elapsed from the time that data is written to a DRAM cell to the time that the data is on the threshold of being corrupted due to charge leakage is referred to as the data retention time of the memory. The longer the data retention time, the less frequently the memory cell needs to be refreshed. Each refresh operation in a DRAM device consumes power. Therefore the longer the data retention time, the lower the required refresh power.
Refresh (or data retention) power is required even when the memory is not being accessed (i.e., when the memory is in a standby mode). Standby mode is defined as a mode in which the memory is not accessed, and some or all of the data stored in the memory is retained. In a power critical application, such as a cell phone, the majority of the power required in standby mode is consumed by performing refresh operations for the DRAM memory. In such an application, it is important to keep the refresh power as low as possible.
A traditional DRAM cell consists of one transistor and one capacitor. Data is stored in a cell in the form of charges in the capacitor. In general, one DRAM cell can store one bit of binary data.
FIG. 1
is a circuit diagram of a traditional DRAM array
100
, in which a plurality of DRAM cells are arranged in rows and columns. DRAM array
100
includes word lines WL
0
-WL
8
and bit lines BL
I
, BL
I#
, BL
I+1
and BL
I+1#
. DRAM array
100
also includes
18
DRAM cells, including DRAM cells
101
-
104
. Each of the DRAM cells includes a capacitor element (represented by a large open square), and an access transistor, which couples the capacitor element to a bit line. The connections between the bit lines and the access transistor drain regions are shown as boxes containing an “X”. For example, DRAM memory cell
101
includes capacitor element
111
and access transistor
112
.
Within array
100
, a column includes a bit-line pair and the associated memory cells. Thus, bit lines BL
I
and BL
I#
and the DRAM cells coupled to these bit lines form one column of array
100
. Bit lines BL
I+1
and BL
I+1#
and the DRAM cells coupled to these bit lines form another column of array
100
. Each memory cell is only coupled to one of the two bit lines in the column. A row consists one cell from each column. Thus, the first row consists of DRAM cells
102
and
104
(which are controlled by word line WL
0
), and the second row consists of the DRAM cells
101
and
103
(which are controlled by word line WL
1
). The configuration of memory array
100
is a well-known folded bit-line architecture.
To perform a memory access, all of the bit lines BL
I
, BL
I#
, BL
I+1
and BL
I+1#
are pre-charged to a fixed voltage. For example, the bit lines can be charged to a voltage equal to half of a supply voltage (V
DD
/2). One of word lines WL
0
-WL
8
is then turned on, thereby connecting one DRAM cell from each column to one of the two bit lines in the column. For example, word line WL
1
can be turned on, thereby coupling DRAM cell
101
to bit line BL
I
(and DRAM cell
103
to bit line BL
I+1
). The charge stored in charge storage element
111
of DRAM cell
101
is shared with bit line BL
I
, and thereby alters the voltage on this bit line. However, the complimentary bit line BL
I#
of the same column remains floating, such that the voltage on this complementary bit line is not directly changed by any DRAM cell charge. Each bit line pair is connected to a sense amplifier, which amplifies the signal difference between the complimentary bit lines. The amplified signals in the bit-line pairs are multiplexed to the data lines through column switches. The difference in the voltage (&Dgr;V) between the complimentary bit lines, before the sense amplifier is turned on, has to overcome any offset in the sense amplifier and any noise that may exist during sensing in order for the data to be sensed accurately. The voltage difference &Dgr;V is dependent mainly on the charge stored in the capacitor element. This charge leaks over time. The longer the refresh period, the greater the charge leakage, and the smaller the voltage difference &Dgr;V. The above-described operating mode of DRAM array is commonly referred to as single-cell mode.
The traditional DRAM array
100
shown in
FIG. 1
can also operate in a differential-cell mode. In the differential-cell mode, two memory cells attached to different bit lines in a column are used to store one bit of binary data. For example, DRAM cell
101
and DRAM cell
102
can be used to store one bit of data in the first column of array
100
. Data is written to a column by pulling one of the column bit lines (e.g., BL
I
) to the V
DD
supply voltage, and the other one of the column bit lines (e.g., BL
I#
) to the ground supply voltage. Therefore, in the differential-cell mode, one DRAM cell (e.g., DRAM cell
101
) stores a voltage of V
DD
in the associated capacitor element, and the other DRAM cell (e.g., DRAM cell
102
) stores a ground voltage in the associated capacitor element. A differential DRAM cell therefore contains two single DRAM cells that store complementary data. During sensing, word lines connected to both DRAM cells (e.g., WL
0
and WL
1
) are turned on, thereby connecting the cells to the complimentary bit lines. Since the DRAM cells are identically constructed, the coupling between the word lines and the bits lines are equal. As a result, any word line to bit-line coupling noise is cancelled during the differential sensing. Likewise, other coupling noise, such as noise in an N-well in which the DRAM cells are contained, is cancelled. More importantly, the differential signal developed across the complementary bit lines is two times larger than the signal developed across the bit lines during the single-cell mode. As a result, the signal strength of a differential DRAM cell is much stronger and thereby can retain the data much longer. It has been shown that the data retention time in differential-cell mode is greater than the data retention time in single-cell mode by a factor of more than 50. (See, U.S. patent application Ser. No. 10/109,878, by Kurjanowicz et al.)
In power critical applications, such as wireless phones and personal data assistants (PDAs), where the devices operate most of the time in the standby mode, the standby power is critical. For devices that include a DRAM array, the standby power is consumed mainly by refresh operations. It is therefore desirable for the DRAM array to have a long data retention time, such that relatively few refresh operations are required during a given time period. When DRAM array
100
operates in the differential-cell mode, the refresh power is significantly less (>25 times less) than the refresh power in single-cell mode. That is, even though the power consumed during a refresh operation in the differential-cell mode is relatively high (because two word lines must be turned on for each refresh operation), the overall refresh power is reduced because the number of refresh operations performed in a given period of time is reduced by a factor of greater than 50. Note that in the differential-cell mode, the storage capacity of the DRAM array is reduced by half (because two DRAM cells are used to store one bit of binary data).
U.S. patent application Ser. No. 10/109,878, by Kurjanowicz et al., and U.S. Pat. No. 5,712,823, by Gillingham describe DRAM memory devices that can be operated in either single-cell mode or differential-cell mode. These DRAM memory devices, as a whole or in parts, c
Jeong Jae-Hong
Leung Wingyu
Bever Hoffman & Harms LLP
Hoffman E. Eric
Monolithic System Technology, Inc.
Phung Anh
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