Method and apparatus for layout synthesis of regular...

Details Method and apparatus for layout synthesis of regular... Method and apparatus for layout synthesis of regular...

2004-06-29

2008-03-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07350174

ABSTRACT:
Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.

REFERENCES:
patent: 5097422 (1992-03-01), Corbin et al.
patent: 5838583 (1998-11-01), Varadarajan et al.
patent: 6237139 (2001-05-01), Patterson et al.
patent: 6243851 (2001-06-01), Hwang et al.
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6594808 (2003-07-01), Kale et al.
patent: 0294188 (1988-12-01), None

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