Method and apparatus for laying out power supply wiring

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06854094

ABSTRACT:
A method for designing power supply wiring of a semiconductor integrated circuit having a logic circuit. A first power consumption value of the logic circuit is calculated based on logic connection information, and the power supply wiring is laid out in accordance with the first power consumption value. Logic modification connection information relating to the modified logic circuit is generated when the logic circuit is modified after the power supply wiring is laid out. A second power consumption value of the modified logic circuit is calculated based on the logic modification connection information. When the second power consumption value exceeds the first power consumption value, it is determined that the power supply wiring must be re-laid out. It is thus easily determined whether to re-lay out the power supply wiring without performing power supply network analysis.

REFERENCES:
patent: 6421816 (2002-07-01), Ishikura
patent: 6493863 (2002-12-01), Hamada et al.
patent: 11-274311 (1999-10-01), None
patent: 2000-020576 (2000-01-01), None
patent: 2000-148833 (2000-05-01), None
patent: 2000-349161 (2000-12-01), None

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