Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-30
2007-01-30
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10420299
ABSTRACT:
An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed. Exemplary gate logic synthesized using the aforementioned methods, and a computer system capable of implementing these methods, are also described.
REFERENCES:
patent: 4763242 (1988-08-01), Lee et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5404319 (1995-04-01), Smith et al.
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5488730 (1996-01-01), Brown et al.
patent: 5491640 (1996-02-01), Sharma et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5502661 (1996-03-01), Glunz
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5537580 (1996-07-01), Giomi et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5555201 (1996-09-01), Dangelo et al.
patent: 5696956 (1997-12-01), Razdan et al.
patent: 5748875 (1998-05-01), Tzori
patent: 5751984 (1998-05-01), Chang et al.
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 5812416 (1998-09-01), Gupte et al.
patent: 5819050 (1998-10-01), Boehling et al.
patent: 5819064 (1998-10-01), Razdan et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5854929 (1998-12-01), Van Praet et al.
patent: 5854930 (1998-12-01), McLain et al.
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5898595 (1999-04-01), Bair et al.
patent: 5994892 (1999-11-01), Turino et al.
patent: 5999734 (1999-12-01), Willis et al.
patent: 6006022 (1999-12-01), Rhim et al.
patent: 6016543 (2000-01-01), Suzuki et al.
patent: 6026219 (2000-02-01), Miller et al.
patent: 6035123 (2000-03-01), Razdan et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6173434 (2001-01-01), Wirthlin et al.
patent: 6182206 (2001-01-01), Baxter
patent: 6195593 (2001-02-01), Nguyen
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6317860 (2001-11-01), Heile
patent: 6321369 (2001-11-01), Heile et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6338136 (2002-01-01), Col et al.
patent: 6360350 (2002-03-01), Gabele et al.
patent: 6378123 (2002-04-01), Dupenloup
patent: 6385757 (2002-05-01), Gupta et al.
patent: 6408428 (2002-06-01), Schlansker et al.
patent: 6421818 (2002-07-01), Dupenloup et al.
patent: 6457173 (2002-09-01), Gupta et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6477697 (2002-11-01), Killian et al.
patent: 6560754 (2003-05-01), Hakewill et al.
patent: 6637018 (2003-10-01), Demler
patent: 6862563 (2005-03-01), Hakewill et al.
patent: 2003/0208723 (2003-11-01), Killian et al.
patent: 0365188 (1990-04-01), None
patent: 2 308 470 (1997-06-01), None
patent: WO 97/13209 (1997-04-01), None
Cambell et al, “A tutorial for make”, Proceedings of the 1985 ACM annual conference on the range of computing; mid-80's perspective, 1985, Denver, Colorado, United States, pp. 374-380, ISBN 0-89791-170-9.
“HDL Chip Design” by Douglas J. Smith, Ninth printing Jul. 2001, minor updates. First Printing Jun. 1996. Doone Publications. ISBN 0-9651934-3-8. pp. 1-25.
Rainer Leupers and Peter Marwedel, Retargetable Code Generation based on Structural Processor Descriptions, Design Automation for Embedded Systems, vol. 3, No. 1, Jan. 1998, p. 1-36.
George Hadjiyiannis, Silvina Hanono, and Scrinivas Devadas, ISDL: An Instruction Set Description Language for Retargetability, 4 pages, 1997.
Vojin Zavojnovic, Stefan Pees, Christian Schlaeger, Markus Willems, Rainer Schoenen and Heinrich Meyr, DSP Processor/Complier Co-Design A Quantitative Approach, Integrated Systems for Signal Processing, Aachen University Technology, p. 761-765, 1998.
Wang et al., “Hardware/Software Instruction Set Configurability for System-on-Chip Processors,” Proceedings of Design Automation Conference, 2001.
Elms, A., “Tuning a Customisable RISC Core for DSP,” Electronic Product Design, Sep. 1997, vol. 18, No. 9, pp. 19-20, 22, XP000909039.
“Custom-Fit Processors: Letting Applications Define Architectures” by Josh Fisher,Paolo Faraboschi, and Giuseppe Desoli.
MDR—Microprocessor Report Article entitled “Tensilica Patents Raise Eyebrows” by Tom R. Halfhill dated Dec. 9, 2002.
Hartoog et al, “Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign,” ACM, Jun. 1997, pp. 303-306.
Freericks “The nML Machine Description Formalism” (Bericht 1991/15 pp. 3-41).
Fauth et al. “Describing Instruction Set Processors Using nML” (Proc. Euro. Design & Test Conf., Paris, Mar. 1995, IEEE 1995, 5 pp.).
Internet Publication http://www.retarget.com/brfchschk.html (19 pp.) No date.
Internet Publication http://www.synopsys.com/products/designware/8051—ds.html (8 pp.) No date.
Internet Publication http://www.synopsys.com/products/designware/dwpci—ds.html (16 pp.) No date.
Internet Publication http://www.lexra.com/product.html (11 pp.) No date.
Internet Publication http://www.risccores.com/html/body—aboutarc.htm (13 pp.) No date.
Clucas, R., “Designing with a Customizable miscroprocessor core,” Electronic Eng'g. vol. 71, No. 865, Feb. 1, 1999, p. 35.
Hogl, H., et al., “Enable + +: A General-Purpose L2 Trigger Processor,” Nuclear Science Symp. & Medical Imaging Conf., vol. 2, Oct. 21-28, 1995, pp. 667-671.
Wollan, V., “A Design Methodology Achieving Fast Development Cycles for Complex VLSI Architectures,” Proc. On the European Conf. on Design Automation, Feb. 22-Mar. 25, 1993, pp. 532-535.
Tensilica, Inc; Xtensa Instruction Set Architecture (ISA) Reference Manual Revision 1.0. (First 25 pages).
Tensilica, Inc. Instruction Extension Language (TIE) Reference Manual Revision 1.3.
Compton et al., “Configurable Computing: A Survey of Systems and Software,” Technical Report, Northwestern University, Dept. of ECE, 1999.
Hauk et al., “The Chimaera Reconfigurable Functional Unit,” Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 1997.
Razdan et al., “A High-Performance Microarchitecture with Hardware-Programmable Function Units,” Proceedings of MICRO-27, Nov. 1997.
Berekovic, Mladen, et al., A Core Generator for Fully Synthesizable and Highly Parameterizable RISC-Cores for System-On-Chip Designs, 1998 IEEE Workshop on Signal Processing Systems, pp. 561-568, XP-002137267.
Yang, Jin-Hyuk, et al., “MetaCore: A Configurable & Instruction-Level Extensible DSP Core,” Proceedings of the ASP-DAC '98 Asian and South Pacific Design Automation Conference 1998, pp. 325-326, XP-002137268.
Warren, H.S., “Instruction Scheduling for the IBM RISC System/6000 Processor,” IBM Journal of Research and Development, vol. 34, No. 1, (1990) pp. 85-92, XP000128183.
“Condition Register Coherency Look-Ahead,” Research Disclosure (1993), No. 348, p. 243, XP000304185.
Ditzel, D.R., et al., “Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero,” 14.sup.th Annual International Symposium on Computer Architecture, (1987), pp. 2-8, XP000212073.
Hakewill James Robert Howard
Sanders John
ARC International
Dinh Paul
Gazdzinski & Associates
LandOfFree
Method and apparatus for jump control in a pipelined processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for jump control in a pipelined processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for jump control in a pipelined processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3798309