Method and apparatus for jitter reduction in phase locked loops

Details Method and apparatus for jitter reduction in phase locked loops Method and apparatus for jitter reduction in phase locked loops

2006-04-04

2006-04-04

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S148000

Reexamination Certificate

active

07023945

ABSTRACT:
A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.

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John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.

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