Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2007-12-11
2007-12-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C710S308000
Reexamination Certificate
active
11054182
ABSTRACT:
A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.
REFERENCES:
patent: 6701417 (2004-03-01), Chaudhry et al.
patent: 2006/0075147 (2006-04-01), Schoinas et al.
Arndt Richard L.
Daly, Jr. George W.
Fields, Jr. James S.
Maule Warren E.
Dillon & Yudell LLP
Dudek Edward J
Gerhardt Diana R.
International Business Machines - Corporation
Kim Matthew
LandOfFree
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