Method and apparatus for invalidating cache lines during...

Details Method and apparatus for invalidating cache lines during... Method and apparatus for invalidating cache lines during...

2005-02-09

2008-11-11

Sorrell, Eron J (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S007000, C710S020000, C710S026000, C711S003000, C711S117000, C711S127000, C711S129000, C711S141000

Reexamination Certificate

active

07451248

ABSTRACT:
A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

REFERENCES:
patent: 5802576 (1998-09-01), Tzeng et al.
patent: 6275909 (2001-08-01), Arimilli et al.
patent: 6535958 (2003-03-01), Fuoco et al.
patent: 6748463 (2004-06-01), Tsuboi et al.
patent: 2004/0158681 (2004-08-01), Hooker

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