Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-12-20
2004-08-03
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S120000, C711S141000, C711S145000, C711S159000
Reexamination Certificate
active
06772298
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention relate to a computer system having a multi-node computer architecture. In particular, the present invention relates to a method and apparatus for invalidating cache lines in a multi-node architecture.
BACKGROUND
Computer systems may contain multiple processors that may work together to perform a task. For example, a computer system may contain four processors that may share system resources (e.g., input devices or memory devices) and may perform parallel processing. The processors may send messages to each other, may send messages to system resources, and may send and receive messages from the system resources. For example, such messages may include requests for information that is stored at a memory location in a memory device.
In many computer systems, the set of data currently being used by a microprocessor may be copied from a system memory device such as a dynamic random access memory (DRAM) into a relatively smaller but faster cache memory device such as a static random access memory (SRAM). The cache memory device is usually private to each processor such that only one processor can read or write to it. As would be appreciated by a person of skill in the art, a “cache line” is a single data entry in a cache memory device (“cache”). That is, a cache line may be the size of the data unit accessed in the cache, in which case the cache line corresponds to a particular block of data in a system memory (“memory block”). A cache line may be said to cache data for a particular memory block if the cache line contains the data element for that memory block. A memory block corresponds to a unit of system memory and may contain one or more data locations (e.g., 32 bytes). A processor may write to a memory block by writing to the corresponding cache line, in which case the cache line and the system memory may contain different values.
A cache is said to be “coherent” if the information resident in the cache reflects a consistent view of the information in all the private cache memory devices and the system memory. If the cache has been updated without updating the system memory, then the system memory is said to contain “stale” data. Similarly, if the system memory has been updated without updating the cache, then the cache is said to contain “stale” data. As discussed above, a cache and a system memory do not always need to contain exact copies of one another. A cache line may be said to be in a “modified” state if has been updated without updating the system memory. If a processor determines that a cache line contains stale data, the processor may “invalidate” that cache line. In some systems, a cache line may be invalidated by setting a flag associated with that cache line to an invalid value. In such systems, when the cache line is invalidated, the cache controller does not use that cache line until a new data element is stored in the cache line.
A processor should not be allowed to use a stale copy of data. Cache “snooping” is one technique used in some systems that have multiple processors to detect the state of a memory location in private cache memory devices on a memory access that might cause a cache coherency problem. Snooping may include the monitoring of a system bus by a first processor to determine if a second processor is accessing a block of system memory that is being cached in the first processor. If a system does not contain a shared bus, processors cannot snoop by monitoring a shared bus, and another method of preventing the use of stale data must be used.
REFERENCES:
patent: 5485579 (1996-01-01), Hitz et al.
patent: 5495419 (1996-02-01), Rostoker et al.
patent: 5535116 (1996-07-01), Gupta et al.
patent: 5541914 (1996-07-01), Krishnamoorthy et al.
patent: 5551048 (1996-08-01), Steely, Jr.
patent: 5557533 (1996-09-01), Koford et al.
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5588131 (1996-12-01), Borrill
patent: 5588132 (1996-12-01), Cardoza
patent: 5588152 (1996-12-01), Dapp et al.
patent: 5590292 (1996-12-01), Wooten et al.
patent: 5590345 (1996-12-01), Barker et al.
patent: 5594918 (1997-01-01), Knowles et al.
patent: 5603005 (1997-02-01), Bauman et al.
patent: 5613136 (1997-03-01), Casavant et al.
patent: 5617537 (1997-04-01), Yamada et al.
patent: 5625836 (1997-04-01), Barker et al.
patent: 5634004 (1997-05-01), Gopinath et al.
patent: 5634068 (1997-05-01), Nishtala et al.
patent: 5636125 (1997-06-01), Rostoker et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5655100 (1997-08-01), Ebrahim et al.
patent: 5657472 (1997-08-01), Van Loo et al.
patent: 5678026 (1997-10-01), Vartti et al.
patent: 5680571 (1997-10-01), Bauman
patent: 5680576 (1997-10-01), Laudon
patent: 5682322 (1997-10-01), Boyle et al.
patent: 5682512 (1997-10-01), Tetrick
patent: 5684977 (1997-11-01), Van Loo et al.
patent: 5699500 (1997-12-01), Dasgupta
patent: 5701313 (1997-12-01), Purdham
patent: 5701413 (1997-12-01), Zulian et al.
patent: 5708836 (1998-01-01), Wilkinson et al.
patent: 5710935 (1998-01-01), Barker et al.
patent: 5713037 (1998-01-01), Wilkinson et al.
patent: 5717942 (1998-02-01), Haupt et al.
patent: 5717943 (1998-02-01), Barker et al.
patent: 5717944 (1998-02-01), Wilkinson et al.
patent: 5734921 (1998-03-01), Dapp et al.
patent: 5734922 (1998-03-01), Hagersten et al.
patent: 5742510 (1998-04-01), Rostoker et al.
patent: 5745363 (1998-04-01), Rostoker et al.
patent: 5749095 (1998-05-01), Hagersten
patent: 5752067 (1998-05-01), Wilkinson et al.
patent: 5754789 (1998-05-01), Nowatzyk et al.
patent: 5754871 (1998-05-01), Wilkinson et al.
patent: 5754877 (1998-05-01), Hagersten et al.
patent: 5761523 (1998-06-01), Wilkinson et al.
patent: 5765011 (1998-06-01), Wilkinson et al.
patent: 5781439 (1998-07-01), Rostoker et al.
patent: 5784697 (1998-07-01), Funk et al.
patent: 5787094 (1998-07-01), Cecchi et al.
patent: 5793644 (1998-08-01), Koford et al.
patent: 5794059 (1998-08-01), Barker et al.
patent: 5796605 (1998-08-01), Hagersten
patent: 5802578 (1998-09-01), Lovett
patent: 5805839 (1998-09-01), Singhal
patent: 5815403 (1998-09-01), Jones et al.
patent: 5842031 (1998-11-01), Barker et al.
patent: 5848254 (1998-12-01), Hagersten
patent: 5857113 (1999-01-01), Muegge et al.
patent: 5860159 (1999-01-01), Hagersten
patent: 5862316 (1999-01-01), Hagersten et al.
patent: 5864738 (1999-01-01), Kessler et al.
patent: 5867649 (1999-02-01), Larson
patent: 5870313 (1999-02-01), Boyle et al.
patent: 5870619 (1999-02-01), Wilkinson et al.
patent: 5875117 (1999-02-01), Jones et al.
patent: 5875201 (1999-02-01), Bauman et al.
patent: 5875462 (1999-02-01), Bauman et al.
patent: 5875472 (1999-02-01), Bauman et al.
patent: 5878241 (1999-03-01), Wilkinson et al.
patent: 5878268 (1999-03-01), Hagersten
patent: 5881303 (1999-03-01), Hagersten et al.
patent: 5887138 (1999-03-01), Hagersten et al.
patent: 5887146 (1999-03-01), Baxter et al.
patent: 5892970 (1999-04-01), Hagersten
patent: 5897657 (1999-04-01), Hagersten et al.
patent: 5900020 (1999-05-01), Safranek et al.
patent: 5903461 (1999-05-01), Rostoker et al.
patent: 5905881 (1999-05-01), Tran et al.
patent: 5905998 (1999-05-01), Ebrahim et al.
patent: 5911052 (1999-06-01), Singhal et al.
patent: 5914887 (1999-06-01), Scepanovic et al.
patent: 5922063 (1999-07-01), Olnowich et al.
patent: 5925097 (1999-07-01), Gopinath et al.
patent: 5931938 (1999-08-01), Drogichen et al.
patent: 5938765 (1999-08-01), Dove et al.
patent: 5941967 (1999-08-01), Zulian
patent: 5943150 (1999-08-01), Deri et al.
patent: 5946710 (1999-08-01), Bauman et al.
patent: 5950226 (1999-09-01), Hagersten et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 5960455 (1999-09-01), Bauman
patent: 5961623 (1999-10-01), James et al.
patent: 5963745 (1999-10-01), Collins et al.
patent: 5963746 (1999-10-01), Barker et al.
patent: 5963975 (1999-10-01), Boyle et al.
patent: 5964886 (1999-10-01), Slaughter et al.
patent: 5966528 (1999-10-01), Wilkinson et al.
patent: 5971923 (1999-10-01), Finger
patent: 5978578 (1999-11-01), Azarya et al.
patent: 5978874 (1999-11-01), Singhal et al.
patent: 59
Cekleov Michel
Creta Ken
George Robert T.
Khare Manoj
Kumar Akhilesh
Elmore Stephen
Kim Matthew
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