Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2001-12-28
2004-03-23
Auve, Glenn A. (Department: 2189)
Electrical computers and digital data processing systems: input/
Interrupt processing
C709S241000
Reexamination Certificate
active
06711643
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an interrupt redirection apparatus and method for inter-processor communication (IPC), and more particularly to an apparatus and method, in which a master processor redirects an interrupt to a slave processor in a system-on-chip (SoC) having two or more ARM processor cores.
BACKGROUND OF THE INVENTION
Generally, in order to construct a multiprocessor system using a plurality of processors, interrupt distribution and inter-processor communication must be supported.
Interrupts are used to inform processors of the occurrence of irregular and exceptional events, and are classified into internal interrupts and external interrupts. Such an internal interrupt is an event occurring in hardware within the processor while the process executes instructions, and occurs in cases such as the execution of a privileged instruction and the generation of overflow of an arithmetic logic unit. Such an external interrupt (hereinafter, referred to as an interrupt) is used for informing processors of the generation of errors of hardware outside the processor, like a peripheral device, and the operation state of peripheral hardware.
The above description of the typical interrupt is disclosed in detail in “Computer System Architecture” by “M. M. Mano” and “Computer Architecture and Organization” by “John P. Hayes”.
A conventional method for informing a processor of an interrupt is to apply an interrupt signal to the processor. Interrupt signals differ from one processor to another, and, for example, for an ARM processor, two interrupt signals composed of a Fast Interrupt Request (FIQ) and an Interrupt ReQuest (IRQ) are provided.
Because the interrupt can be generated in a variety of peripheral devices outside the processor, an interrupt controller is used for collecting interrupt signals received from a plurality of interrupt sources and sending the interrupt signals to the processor as interrupt request signals.
In a multiprocessor system using a plurality of processors, inter-processor communication is required. In the multiprocessor system, the processors divide a specific task and process the divided operations simultaneously. At this time, inter-processor communication is required for performing the synchronization between processors and informing the processors of status thereof. Here, a common variable method that sets the threshold region in a shared memory and constructs a common variable in the threshold region, and a message passing method that constructs a specific communication channel between processors, and transmits/receives messages through the communication channel are used in the inter-processor communication.
The communication method using the common variable is used in the multiprocessor system employing the shared memory and can be realized using only software without additional hardware devices. On the other hand, the message passing method uses a communication channel provided by hardware regardless of the sharing of the memory.
The above description of the conventional inter-processor communication is disclosed in detail in “Advanced Computer Architecture, Parallelism, Scalability, Programmability” by “Kai Whang”.
The ARM (Advanced RISC Machines) processor does not provide a multiprocessor function, for example, interrupt redistribution and communication channel hardware according to its structural characteristics. Further, in a “PrimeCell”, which is a semiconductor library provided by ARM Corporation, design resources for supporting the multiprocessor are not supported.
Meanwhile, conventional technologies related to the interrupt distribution and the inter-processor communication are described as follows.
The ARM Corporation provides an interrupt controller named a Vectored Interrupt Controller (VIC) which performs a vectored interrupt control function so as to design an ARM processor based system-on-chip. The vectored interrupt controller collects interrupts generated in a plurality of peripheral devices and transfers the interrupts to the IRQ and FIQ which are interrupt reception signals of the ARM processor using a point-to-point connection method. The vectored interrupt controller is an interrupt controller for a single ARM processor, and is disadvantageous in that, when it is adapted to a design structure having a plurality of ARM processors therein, each exclusive vectored interrupt controller must be connected to each ARM processor. Further, the vectored interrupt controller is problematic in that, because the same interrupt source is connected to a plurality of vectored interrupt controllers, it is not clear which processor must process a generated interrupt, thus causing a problem in software development. In a design structure using a plurality of ARM processors, the inter-processor communication must be supported, and in the inter-processor communication, the message passing method for asynchronously transferring messages to the processor as well as the communication using a predetermined region of the shared memory must be supported. In order to perform an asynchronous inter-processor communication, a function for requesting an interrupt between processors is required. However, the vectored interrupt controller provided by the ARM Corporation is problematic in that it must employ a plurality of vectored interrupt controllers so as to allow mutual communication between the processors.
Further, U.S. Pat. No. 6,189,065 B1 owned by IBM Corporation discloses the invention entitled “Method and Apparatus for interrupt load balancing for PowerPC processors”, as described below in detail.
In the above patent, interrupt buses between processors are constructed in the form of a “Daisy-chain” using interrupt reception and transmission hardware devices included in a processor. Further, an interrupt queue and a counter are included in the processor. The above patent primarily claims hardware having a function such that if an interrupt is transferred to a specific processor, the hardware confirms the interrupt counter in the processor and transmits the interrupt to an interrupt reception unit of the processor adjacent to the specific processor with the “Daisy-chain” construction if the counted value exceeds a predetermined number, and an interrupt load distribution method utilizing the hardware. However, the invention of the patent is disadvantageous in that the interrupt transmission and reception hardware devices are additionally constructed inside or outside each processor, interrupt transmission and reception units between adjacent processors are connected to each other with the “Daisy-Chain” construction, and especially, an additional interrupt bus must be constructed so as to transmit/receive an interrupt between processors. Consequently, the invention cannot be applied to design structures using ARM processors.
Further, U.S. Pat. No. 6,237,058 B1 owned by NEC Corporation discloses the invention entitled “Interrupt load distribution system for shared bus type multiprocessor systems and interrupt load distribution method”, as described below in detail.
Referring to the patent, in common bus based multiprocessor systems, the operating system (OS) stores interrupt processing load details according to processors through a table managing interrupt processing statistics according to processors. The operating system constructs an interrupt scheduling information table therein on the basis of the interrupt statistics table according to processors. The interrupt scheduling information table is used as a table for determining which processor processes a corresponding interrupt according to kinds of interrupts.
In order to perform an interrupt scheduling operation, an input/output controller has an interrupt target information table for designating target processors according to interrupts therein, and the operating system periodically updates the interrupt target information table to uniformly distribute interrupts to each processor.
The above patent primarily claims a method for adding a function for managing interr
Kim Yong Youn
Moh Sang Man
Park Kyoung
Auve Glenn A.
Electronics and Telecommunications Research Institute
Holman PLLC Jacobson
Lee Christopher E.
LandOfFree
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