Patent
1997-06-03
1999-04-06
Ray, Gopal C.
395733, G06F 1314, G06F 1324, G06F 946
Patent
active
058929576
ABSTRACT:
An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
REFERENCES:
patent: 4228503 (1980-10-01), Waite et al.
patent: 4604500 (1986-08-01), Brown et al.
patent: 4734882 (1988-03-01), Romagosa
patent: 4953072 (1990-08-01), Williams
patent: 5036459 (1991-07-01), den Haan et al.
patent: 5319753 (1994-06-01), MacKenna et al.
patent: 5325536 (1994-06-01), Chang et al.
patent: 5428799 (1995-06-01), Woods et al.
patent: 5481726 (1996-01-01), Kumaki et al.
patent: 5542076 (1996-07-01), Benson et al.
patent: 5557744 (1996-09-01), Kobayakawa et al.
patent: 5701495 (1997-12-01), Arndt et al.
Lantz, Keith, et al., "Rochester's Intelligent Gateway", Computer, vol. 15, No. 10, Oct. 1982, pp. 54-68.
Alpert, D., et al., "Architecture of the NS32532 Microprocessor", 1987 IEEE International Conference on Computer Design, Oct. 5-8, 1987, pp. 168-172.
Chang, Jung-Herng, et al., "A Second-Level Cache Controller for A Super-Scalar SPARC Processor", 37th IEEE Computer Society International Conference, Feb. 24-28, 1992, pp. 142-151.
Cvijovic, Miomirka, et al., "An approach to the design of distributed real-time operating systems", Microprocessors and Microsystems, vol. 16, No. 2, 1992, pp. 81-89.
Weaver, David L., et al. "The SPARC Architecture Manual", Version 9, 1994, pp. 117-129, 256-262.
Chen Sun-Den
Ebrahim Zahir
Narad Charles E.
Nishtala Satyanarayana
Normoyle Kevin B.
Ray Gopal C.
Sun Microsystems Inc.
Williams Gary S.
LandOfFree
Method and apparatus for interrupt communication in packet-switc does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for interrupt communication in packet-switc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for interrupt communication in packet-switc will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1380082