Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1999-03-23
2001-11-20
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C710S058000, C713S501000
Reexamination Certificate
active
06321342
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to interfacing a circuit with another circuit, and more particularly to interfacing a circuit with other circuits operating at different frequencies.
With the growing trend toward IP reuse via core-based design styles, managing clock domains becomes an increasing challenge. Quite often, the different IP cores in a design operate on different clock domains, and interfacing these cores together can require additional synchronization adding to the complexity of the design, and possibly reducing performance.
For example, a RAID SCSI host adapter commonly utilizes more than one clock domain. A RAID SCSI host adapter essentially provides an interface between a computer system and a RAID storage device. Moreover, a RAID SCSI host adapter is commonly implemented as an expansion card which may be inserted into an expansion slot of a computer system.
Commonly the expansion slot of a computer system provides expansion boards access to the system bus of the computer system. A common system bus in present computer systems is the PCI Local Bus. The PCI Local Bus Specification, Rev. 2.1 defines protocol, electrical, mechanical, and configuration specifications for PCI Local Bus components and expansion boards. One such requirement is that the PCI Local Bus be implemented as a synchronous bus which operates based upon a 33 MHz clock signal or a 66 MHz clock signal. Due to these requirements, the PCI Local Bus Specification forces expansion boards such as a RAID SCSI host adapter to include PCI interface circuitry that operates based upon the same 33 MHz or 66 MHz clock signal provided by the PCI Local Bus.
Besides PCI interface circuitry that operates based upon a 33 MHz clock signal, a RAID SCSI host adapter typically also includes a SCSI controller integrated circuit device (i.e. a SCSI control chip), a DRAM (dynamic random access memory) controller, and on-board DRAM. The DRAM controller and on-board DRAM typically must operate based upon a clock signal having a frequency for which the DRAM controller and DRAM were designed. More specifically, if the DRAM controller and DRAM are designed to be operated based upon a 40 MHz clock, then the DRAM controller and DRAM must be operate based upon a 40 MHz clock signal. Operating the DRAM controller and DRAM based upon a faster clock signal such as a 66 MHz clock signal would likely violate setup-and-hold times and/or signal propagation times of the DRAM controller and DRAM, thus resulting in data integrity errors and sporadic behavior. Similarly, operating the DRAM controller and DRAM based upon a slower clock signal such as a 33 MHz clock signal would cause the refresh circuitry of the DRAM controller to refresh the DRAM contents at a slower rate than the DRAM was designed. As a result of refreshing the DRAM at a slower rate, data integrity errors are likely to occur due to stored charges leaking faster than the refresh circuitry of the DRAM controller can recharge them. Accordingly, the RAID SCSI host adapter typically includes an on-board oscillator or other mechanism for providing the DRAM controller and DRAM with a clock signal having an appropriate frequency such as 40 MHz.
During operation of the RAID SCSI host adapter, the SCSI control chip must access the PCI bus via the PCI interface circuitry and the DRAM via the DRAM controller. Since the PCI interface circuitry operates based upon a first clock signal having a frequency of 33 MHz and the DRAM controller operates based upon a second clock signal having a frequency of 40 MHz, the RAID SCSI host adapter must include circuitry that properly interfaces the SCSI control chip with the PCI interface circuitry and the DRAM controller.
One such scheme for interfacing a circuit such as the SCSI control chip with two circuits operating based upon clock signals having different frequencies is taught by Charneski et al. (U.S. Pat. No. 5,680,594). Charneski teaches the use of an ASIC bus interface
20
for interfacing a first circuit such as a microprocessor with a first subsystem
22
and a second subsystem
24
that are operating based upon different clock signals. While this scheme is sufficient in many environments it suffers from several short comings. As illustrated in
FIG. 1
, the ASIC bus interface
20
includes a separate synchronizing state machine
12
,
14
,
16
,
18
for each different clock signal. This results in a rather large die size for the ASIC bus interface
20
if several different clock signals are required because the ASIC bus interface
20
must include a separate synchronizing state machine
12
,
14
,
16
,
18
for each different clock signal.
Moreover, the ASIC bus interface
20
introduces an additional layer of circuitry between the microprocessor and the subsystems
22
,
24
. As a result of this additional layer of circuitry, ASIC bus interface
20
includes additional logic to ensure that a data overflow condition does not occur due to the microprocessor transferring data to a subsystem
22
,
24
at a rate faster than the ASIC bus interface
20
can transfer the data to the destined subsystem
22
,
24
. In particular, the ASIC bus interface
20
includes bus cycle clock logic
19
which generates a bus cycle done signal after the data is transferred to the appropriate subsystem
22
,
24
. Unless the ASIC bus interface
20
includes substantial buffer memory and additional logic to ensure that a data overflow condition does not occur, the microprocessor must wait until it receives the bus cycle done signal before transferring additional data to the desired subsystem
22
,
24
. As a result of (i) waiting for the bus cycle done signal, and (ii) the processing required by the ASIC bus interface
20
to generate the bus cycle done signal, the microprocessor is unable to interface the desired subsystem in a synchronous manner thereby inhibiting the microprocessor from transfer data to the desired subsystem during each clock cycle of the clock signal upon which the desired subsystem operates.
What is needed therefore is an interfacing method and apparatus which is operable to provide a circuit with a synchronous interface for interfacing circuits operating based upon different clock signals.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided a method of interfacing a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal with a third circuit. One step of the method includes transferring first signals between the third circuit and the first circuit. Another step of the method includes operating the third circuit based upon the first clock signal during the step of transferring the first signals between the third circuit and the first circuit. Yet another step of the method includes transferring second signals between the third circuit and the second circuit. The method also includes the step of operating the third circuit based upon the second clock signal during the step of transferring the second signals between the third circuit and the second circuit.
Pursuant to another embodiment of the present invention, there is provided a method of interfacing a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal with a third circuit. One step of the method includes applying the first clock signal and the second clock signal to a clock selector for the third circuit. The method further includes the step of transferring first data signals between the third circuit and the first circuit at a first rate based upon the first clock signal. Another step of the method includes causing the clock selector to apply the first clock signal to the third circuit prior to the step of transferring the first data signals between the third circuit and the first circuit. Yet another step of the method includes transferring second data signals between the third circuit and the second circuit at a second rate based upon the second
Day Brian A.
Hoglund Timothy E.
Heckler Thomas M.
LSI Logic Corporation
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