Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-22
2007-05-22
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10387644
ABSTRACT:
A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
REFERENCES:
patent: 5629859 (1997-05-01), Agarwala et al.
patent: 5663662 (1997-09-01), Kurosawa
patent: 5726903 (1998-03-01), Kerzman et al.
patent: 5901063 (1999-05-01), Chang et al.
patent: 5923564 (1999-07-01), Jones, Jr.
patent: 5984510 (1999-11-01), Guruswamy et al.
patent: 6058252 (2000-05-01), Noll et al.
patent: 6145117 (2000-11-01), Eng
patent: 6263478 (2001-07-01), Hahn et al.
patent: 6360356 (2002-03-01), Eng
patent: 6381730 (2002-04-01), Chang et al.
patent: 6427226 (2002-07-01), Mallick et al.
patent: 6493856 (2002-12-01), Usami et al.
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 6687890 (2004-02-01), Sato
patent: 6698006 (2004-02-01), Srinivasan et al.
NN950127 (“Algorithm for Incremental Timing Analysis”, IBM Technical Disclosure Bulletin, vol. 38, No. 1, Jan. 1995, pp. 27-34 (18 pages)).
Almusa Hazem
Kaufman Douglas
Ke Larry
Li Wei
Mathews Robert
Bowers Brandon
Chiang Jack
MacPherson Kwok & Chen & Heid LLP
Sequence Design, Inc.
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