Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-08-15
2000-05-30
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714726, 714733, 714734, G06F 1127
Patent
active
060702524
ABSTRACT:
Methods and apparatus for interactive built-in self-testing with user-programmable test patterns are disclosed. The present invention operates in the context of an integrated circuit (IC) including built-in self-test (BIST) logic and a test interface circuit resident on the IC. The BIST logic executes a BIST routine for testing the IC, and the test interface achieves the inputting of an external test pattern into the BIST logic from an external logic circuit. The test interface includes a first flag storage element accessible to the BIST logic. The first flag storage element stores a first flag that indicates whether the test pattern will be provided to the IC from the external logic. A test data storage element in the test interface stores the external test pattern, and is also accessible to the BIST logic. A second flag storage element accessible to the BIST logic stores a second flag to indicate whether the test pattern is available in the test data storage element. Test control logic receives a first instruction from the external logic, and executes the first instruction to set the first flag. The test control logic reads the test pattern and sets the second flag after the test pattern is stored in the test data storage element. If the first flag is not set, the BIST logic executes the BIST routine using a test pattern internally generated on the IC. On the other hand, if the first flag is set, then the BIST logic executes the BIST routine using the test patterns stored in the test data storage element.
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Lakhani Murtuza Ali
Xu Yan
Baderman Scott T.
Beausoliel, Jr. Robert W.
Intel Corporation
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