Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-03-08
2011-03-08
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S100000, C716S101000, C703S013000, C703S014000
Reexamination Certificate
active
07904870
ABSTRACT:
A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
REFERENCES:
patent: 4266270 (1981-05-01), Daniels
patent: 5263153 (1993-11-01), Intrater
patent: 5723962 (1998-03-01), Mizukami et al.
patent: 5752013 (1998-05-01), Christensen
patent: 5938760 (1999-08-01), Levine
patent: 5961654 (1999-10-01), Levine
patent: 6047367 (2000-04-01), Heller
patent: 6085338 (2000-07-01), Levine
patent: 6295623 (2001-09-01), Lesmeister et al.
patent: 6351844 (2002-02-01), Bala
patent: 6466898 (2002-10-01), Chan
patent: 6912673 (2005-06-01), Wyland
patent: 7020678 (2006-03-01), Hubbard
patent: 7694303 (2010-04-01), Hahn et al.
patent: 7802236 (2010-09-01), Calder et al.
patent: 2002/0116166 (2002-08-01), El-Ghoroury
patent: 2004/0068701 (2004-04-01), Chang et al.
patent: 2004/0111708 (2004-06-01), Calder
patent: 2004/0216013 (2004-10-01), Sun
patent: 2007/0157177 (2007-07-01), Bouguet
patent: 2009/0182994 (2009-07-01), Bell et al.
patent: 2009/0183127 (2009-07-01), Bell, Jr.
patent: 2009/0199138 (2009-08-01), Bell et al.
patent: 2009/0276190 (2009-11-01), Bell et al.
patent: 04184678 (1992-07-01), None
Wikipedia—“K-Means Algorithm”—Online Wikipedia Reference Material (Dec. 2007).
Robinson—“Initial Starting Point Analysis for K-Means clustering: A Case Study”—Proceedings of ALAR 2006 Conference on Applied Research in Information Technology (Mar. 2006.)
Hamerly-1—“SimPoint 3.0: Faster and More Flexible Program Analysis”—Dept Computer Science and Engineering UC San Diego (Sep. 2005).
Hamerly-2—“How to Use SimPoint to Pick Simulation Points”—Dept Computer Science and Engineering UC San Diego (Mar. 2004).
Anderson—“Continuous Profiling: Where Have All the Cycles Gone?”—Digital Equipment Corporation (Oct. 13, 1999).
Eyerman—“A Performance Counter Architecture for Computing Accurate CPI Components”—Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (2006).
AZIMI—“Online Performance Analysis by Statistical Sampling of Microprocessor Performance Counters”—Proceedings of the 19th Annual International Conference on Supercomputing (2005).
Luo—“Automatically Selecting Representative Traces for Simulation Based on Cluster Analysis of Instruction Address Hashes”—The University of Texas at Austin IBM Server Group (2005).
Wunderlich-1—“An Evaluation of Stratified Sampling of Microarchitecture Simulations”—Computer Architecture Laboratory ISCA-31 (Jun. 2004).
Wunderlich-2—“Smarts: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling”—International Symposium on Computer Architecture ISCA-30 (Jun. 2003).
Wunderlich-3—“TurboSmarts: Accurate Microarchitecture Simulation Sampling in Minutes”—Computer Architecture Lab at Carnegie Mellon CALCM (2004).
Taufer—“Scalability and Resource Usage of an OLAP Benchmark on Cluster of PCs”—Proceedings of 14th Annual ACM Symposium on Parallel Algorithms and Architectures (2002).
Puzak—“An Analysis of the Effects of Miss Clustering on the Cost of a Cache Miss”—IBM SIGMICRO—(2007).
Annavaram—“The Fuzzy Correlation between Code and Performance Predictability”—Proceedings of the 37th International Symposium on Microarchitecture (2004).
Lau-1—“Transition Phase Classification and Prediction”—11th International Symposium on High Performance Computer Architecture, Feb. 2005.
Lau-2—“The Strong Correlation Between Code Signatures and Performance”—IEEE International Symposium on Performance Analysis of Systems and Software, Mar. 2005.
Laurenzano—“Low Cost Trace-driven Memory Simulation Using SimPoint”—Workshop on Binary Instrumentation and Applications (held in conjunction with PACT2005), St. Louis, MO Sep. 2005.
Pereira—“Dynamic Phase Analysis for Cycle-Close Trace Generation”—International Conference on Hardware/Software Codesign and System Synthesis, Sep. 2005.
Sherwood-1—“Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications” In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2001.
Sherwood-2—“Automatically Characterizing Large Scale Program Behavior”—Architectural Support for Programming Languages and Operating Systems ASPLOS at University of California, San Diego (2002).
Lyengar—“Representative Traces For Processor Models with Infinite Cache”—IBM Research Division presented at the International Symposium on High Performance Computer Architecture HPCA (2005).
Perelman—“Picking Statistically Valid and Early Simulation Points”—Proceedings of the International Conference on Parallel Architectures and Compilation Techniques PACT (Sep. 2003).
SimPoint—“SimPoint Overview”—downloaded from http://www.cse.ucsd.edu/˜calder/simpoint/phase—analysis.htm on Oct. 20, 2007.
Bhargava—“Improving Dynamic Cluster Assignment for Clustered Trace Cache Processor”—The University of Texas at Austin and 2003 Annual International Symposium on Computer Architecture (Jun. 2003).
Chen—“Nonlinear Adaptive Distance Metric Learning for Clustering”—Department of Computer Science and Engineering Arizona State University (Aug. 2007).
Taylor—“The use of Process Clustering in Distributed-System Event Displays”—Proceeding of the 1993 CAS Conference (1993).
Hong—“Cluster-Based Input/Output Trace Synthesis” 24th IEEE International Performance, Computing, and Communications Conference, 2005. IPCCC 2005.
Bell, Jr. Robert H.
Chen Wen-Tzer Thomas
Indukuru Venkat Rajeev
Seshadri Pattabi Michael
Valluri Madhavi Gopal
Doan Nghia M
International Business Machines - Corporation
Kahler Mark P
Talpis Matt
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