Method and apparatus for integrated circuit datapath layout...

Details Method and apparatus for integrated circuit datapath layout... Method and apparatus for integrated circuit datapath layout...

2008-05-20

2008-05-20

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07376922

ABSTRACT:
A vector editor for providing an integrated circuit datapath layout. For one aspect, vectors may be extracted from an integrated circuit design input file using a name-based vector extraction approach, a bus/connectivity-based vector extraction approach or another approach. Each vector may be represented as one of a row and a column, wherein the representation differs from that of the associated physical layout. Each bit slice associated with the integrated circuit layout is represented in an orthogonal manner to the vectors. For one aspect, instances of similar master cells may be represented using similar visual representations.

REFERENCES:
patent: 5838583 (1998-11-01), Varadarajan et al.
patent: 6237129 (2001-05-01), Patterson et al.
patent: 6757878 (2004-06-01), Srinivasan et al.
patent: 6792585 (2004-09-01), Ku et al.
patent: 2003/0126571 (2003-07-01), Srinivasan et al.

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