Electrical computers and digital processing systems: processing – Instruction issuing
Patent
1996-12-19
1999-12-21
Vu, Viet D.
Electrical computers and digital processing systems: processing
Instruction issuing
712216, G06F 938
Patent
active
060063254
ABSTRACT:
A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.
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Bryg William R.
Burger Stephen
Hammond Gary N.
Institute for the Development of Emerging Architectures L.L.C.
Vu Viet D.
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