Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration – Loading initialization program
Reexamination Certificate
1999-07-28
2004-02-03
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
Loading initialization program
Reexamination Certificate
active
06687818
ABSTRACT:
TRADEMARK NOTICES
Unix is a registered trademark of The Open Group. SCO and Unixware are registered trademarks of The Santa Cruz Operation, Inc. Microsoft, Window, Window NT and/or other Microsoft products referenced herein are either trademarks or registered trademarks of Microsoft Corporation. Intel, Pentium, Pentium II Xeon, Pentium III Xeon, Merced and/or other Intel products referenced herein are either trademarks or registered trademarks of Intel Corporation.
TECHNICAL FIELD OF THE INVENTION
This invention relates to multiprocessing data processing systems, and more particularly to symmetrical multiprocessor data processing systems that have a clustered processor architecture. More specifically, the present invention relates to a method and apparatus for booting such clustered multiprocessor systems, and for initiating execution of selected application processors within such systems.
BACKGROUND OF THE INVENTION
Systems having multiple but coordinated processors were first developed and used in the context of mainframe computer systems. More recently, however, interest in multiprocessor systems has increased because of the relatively low cost and high performance of microprocessors, with the objective of replicating mainframe performance through the parallel use of multiple microprocessors.
A variety of architectures have been developed including a symmetrical multiprocessing (“SMP”) architecture, which is used in many of today's workstation and server markets. In SMP systems, the processors have symmetrical access to all system resources such as memory, mass storage and I/O.
The operating system typically handles the assignment and coordination of tasks between the processors. Preferably the operating system distributes the workload relatively evenly among all available processors. Accordingly, the performance of many SMP systems may increase, at least theoretically, as more processor units are added. This highly sought-after design goal is called scalability.
One of the most significant design challenges in many multiprocessor systems is the routing and processing of interrupts. An interrupt may generally be described as an event that indicates that a certain condition exists somewhere in the system that requires the attention of at least one processor. The action taken by a processor in response to an interrupt is commonly referred to as the “servicing” or “handling” of the interrupt. Each interrupt typically has an identity that distinguishes it from the others. This identity is often referred to as the “vector” of the interrupt. The vector allows the servicing processor or processors to find the appropriate handler for the interrupt. When a processor accepts an interrupt, it uses the vector to locate the entry point of the handler in a pre-stored interrupt table.
In some multiprocessor systems, a central interrupt controller is provided to help route the interrupts from an interrupt source to an interrupt destination. In other systems, the interrupt control function is distributed throughout the system. In a distributed interrupt control architecture, one or more global interrupt controllers assumes global, or system-level, functions such as, for example, I/O interrupt routing. A number of local interrupt controllers, each of which is associated with a corresponding processing unit, controls local functions such as, for example, inter-processor interrupts. Both classes of interrupt controllers typically communicate over a common interrupt bus, and are collectively responsible for delivering interrupts from an interrupt source to an interrupt destination within the system.
The Intel Corporation published a Multiprocessor (MP) specification (version 1.4) outlining the basic architecture of a standard multiprocessor system that uses Intel brand processors. Complying with the Intel Multiprocessor (MP) specification may be desirable, particularly when Intel brand processors are used. According to the Intel Multiprocessor (MP) Specification (version 1.4), interrupts are routed using one or more Intel Advanced Programmable Interrupt Controllers (APIC). The APICs are configured into a distributed interrupt control architecture, as described above, where the interrupt control function is distributed between a number of local APIC and I/O APIC units. The local and I/O APIC units communicate over a common bus called an Interrupt Controller Communications (ICC) bus. There is one local APIC per processor and, depending on the total number of interrupt lines in an Intel MP compliant system, one or more I/O APICs. The APICs may be discrete components separate from the processors, or integrated with the processors.
The destination of an interrupt can be one, all, or a subset of the processors in the Intel MP compliant system. The sender specifies the destination of an interrupt in one of two destination modes: physical destination mode or logical destination mode. In physical destination mode, the destination processor is identified by a local APIC ID. The local APIC ID is then compared to the local APIC's actual physical ID, which is stored in a local APIC ID register within the local APIC. A bit-wise definition of the local APIC ID register is shown in FIG.
1
. The local APIC ID register is loaded at power up by sampling configuration data that is driven onto pins of the processor. For the Intel P6 family processors, pins A
11
# and A
12
# and pins BR
0
# through BR
3
# are sampled. Up to 15 local APICs can be individually addressed in the physical destination mode.
The logical destination mode can be used to increase the number of APICs, and thus, processors, that can be individually addressed by the system. In the logical destination mode, message destinations are identified using an 8-bit message destination address (MDA). The MDA is compared against the 8-bit logical APIC ID field of the APIC logical destination register (LDR). A bit-wise definition of the logical destination register is shown in FIG.
2
.
A Destination Format Register (DFR) is used to define the interpretation of the logical destination information. A bit-wise definition of the destination format register is shown in FIG.
3
. The DFR register can be programmed for a flat model or a cluster model interrupt delivery mode. In the flat model delivery mode, bits
28
through
31
of the DFR are programmed to 1111. The MDA is then interpreted as a decoded address. This delivery mode allows the specification of arbitrary groups of local APICs by simply setting each APIC's corresponding bit to
1
in the corresponding LDR. Broadcast to all APICs is achieved by setting all 8 bits of the MDA to one. As can be seen, the flat model only allows up to 8 local APICs to coexist in the system.
FIG. 4
is a block diagram of an illustrative multiprocessor system connected in accordance with the flat model delivery mode described in the Intel Multiprocessor (MP) specification (version 1.4).
For the cluster model delivery mode, the DFR bits
28
through
31
are programmed to 0000. In this delivery mode, there are two basic connection approaches: a flat cluster approach and a hierarchical cluster approach. In the flat cluster approach, it is assumed that all clusters are connected to a single APIC bus (e.g., ICC bus).
FIG. 5
is a block diagram of an illustrative multiprocessor system connected in accordance with the flat cluster model delivery mode described in the Intel Multiprocessor (NV) specification (version 1.4). In this mode, bits
28
through
31
of the MDA contain the encoded address of the destination cluster. These bits are compared with bits
28
through
31
of the LDR (see
FIG. 2
) to determine if the local APIC is part of the cluster. Bits
24
through
27
of the MDA are compared with Bits
24
through
27
of the LDR to identify the individual local APIC unit within the selected cluster.
Arbitrary sets of processors within a cluster can be specified by writing the target cluster address in bits
28
through
31
of the MDA and setting selected bits in bits
24
through
27
Erickson Philip J.
Miller John A.
Morrissey Doug E.
Svenkeson Penny L.
Wilson Peter C.
Butler Dennis M.
Crompton Seager & Tufte LLC
Johnson Charles A.
Starr Mark T.
Unisys Corporation
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