Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-04-15
2008-04-15
Lane, Jack (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000
Reexamination Certificate
active
07360027
ABSTRACT:
An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.
REFERENCES:
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 6460115 (2002-10-01), Kahle et al.
patent: 6473832 (2002-10-01), Ramagopal et al.
patent: 6711651 (2004-03-01), Moreno et al.
patent: 6922753 (2005-07-01), Brown et al.
patent: 7010666 (2006-03-01), Barber et al.
patent: 7231470 (2007-06-01), Huggahalli et al.
patent: 7246205 (2007-07-01), Balakrishnan et al.
patent: 2004/0064648 (2004-04-01), Brown et al.
patent: 2004/0117606 (2004-06-01), Wang et al.
patent: 2004/0128450 (2004-07-01), Edirisooriya et al.
patent: 2004/0199727 (2004-10-01), Narad
patent: 2005/0132102 (2005-06-01), Huggahalli et al.
patent: 2005/0154836 (2005-07-01), Steely et al.
patent: 2005/0246500 (2005-11-01), Iyer et al.
patent: 2005/0289303 (2005-12-01), Jamil et al.
patent: 2006/0064518 (2006-03-01), Bohrer
patent: 2006/0095679 (2006-05-01), Edirisooriya
patent: 2006/0136671 (2006-06-01), Yavaykar et al.
Ram Huggahalli et al., “Dynamically Setting Routing Information to Transfer Input Output Data Directly into Processor Caches in a Multi Processor System,” U.S. Appl. No. filed on Dec. 16, 2003.
PCT/US2005/037165 Int'l Search Report & Written Opinion.
Office Action in corresponding matter U.S. Appl. No. 10/977,830, filed Oct. 28, 2004, to S. Edirisooriya, dated Mar. 7, 2007.
Office Action in corresponding matter U.S. Appl. No. 10/736,765, filed Dec. 16, 2003, to R. Huggahalli, dated Jan. 17, 2006.
Office Action in corresponding matter U.S. Appl. No. 10/736,765, filed Dec. 16, 2003, 2003, to R. Huggahalli, dated Jun. 19, 2006.
Office Action in corresponding matter U.S. Appl. No. 10/736,765, filed Dec. 16, 2003, R. Huggahalli, dated Nov. 13, 2003.
Office Action in corresponding matter U.S. Appl. No. 11/021,143, filed Dec. 22, 2004, to B. Balakrishnan, dated Jan. 23, 2007.
Office Action in corresponding matter U.S. Appl. No. 11/021,143, filed Dec. 22, 2004, to B. Balakrishnan, dated Apr. 18, 2007.
Office Action in corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad, dated Oct. 5, 2005.
Office Action in corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad, dated Jul. 12, 2006.
Office Action in corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad dated Mar. 16, 2006.
Office Action in corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad, dated Apr. 4, 2005.
Office Action in corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad, dated Sep. 15, 2006.
Office Action in corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad, dated Dec. 7, 2006.
Office Action dated Aug. 23, 2005, for corresponding matter U.S. Appl. No. 10/323,989, filed Dec. 17, 2002, to H. Wong et al.
Office Action dated Apr. 5, 2006, for corresponding matter U.S. Appl. No. 10/323,989, filed Dec. 17, 2002, to H. Wong et al.
Office Action dated Jan. 10, 2007, for corresponding matter U.S. Appl. No. 10/323,989, filed Dec. 17, 2002, to H. Wong et al.
Office Action dated May 22, 2007, for corresponding matter U.S. Appl. No. 10/406,798, filed Apr. 2, 2003, to C. Narad et al.
Office Action dated Jun. 6, 2005, for corresponding matter U.S. Appl. No. 10/331,688, filed Dec. 30, 2002, to Edirisooriya et al.
Office Action dated Nov. 30, 2005, for corresponding matter U.S. Appl. No. 10/331,688, filed Dec. 30, 2002, to Edirisooriya et al.
Notice of Allowance dated Mar. 22, 2007, for corresponding matter U.S. Appl. No. 10/736,765, filed Dec. 16, 2003, to R. Huggahalli et al.
Notice of Allowance dated May 22, 2007, for corresponding matter U.S. Appl. No. 11,021,143, filed Dec. 22, 2004, to Balakrishnan et al.
Batson Brannon J.
Blankenship Robert G.
Huggahalli Ramakrishna
Tetrick Raymond S.
Intel Corporation
Lane Jack
Zhou Guojun
LandOfFree
Method and apparatus for initiating CPU data prefetches by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for initiating CPU data prefetches by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for initiating CPU data prefetches by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2771928