Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1998-04-28
2001-01-23
Beausoliel, Jr., Robert W. (Department: 2785)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S002000, C711S166000, C714S023000
Reexamination Certificate
active
06178501
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to integrated circuit memory devices, and more particularly, to a method and apparatus for initializing a memory device in preparation for operation of the memory device.
BACKGROUND OF THE INVENTION
A conventional memory device is illustrated in FIG.
1
. The memory device is a synchronous dynamic random access memory (“SDRAM”) that includes an address register
12
receiving either a row address and a bank address bit or a column address on an address bus
14
. The address bus
14
is generally coupled to a memory controller (not shown in FIG.
1
). Typically, a row address and a bank address are received by the address register
12
, and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to one of two row address latches
26
depending on the state of the bank address bit. Each of the row address latches
26
stores the row address, and applies it to a row decoder
28
, which applies various signals to a respective memory bank array
20
,
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
26
for the purpose of refreshing memory cells in the arrays
20
,
22
. The row addresses are generated for refresh purposes by a refresh counter
30
that is controlled by a refresh controller
32
. The arrays
20
,
22
are comprised of memory cells arranged in rows and columns.
After the row address has been applied to the address register
12
and stored in one of the row address latches
26
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
40
. Depending on the operating mode of the SDRAM
10
, the column address is either coupled through a burst counter
42
to a column address buffer
44
, or to the burst counter
42
, which applies a sequence of column addresses to the column address buffer
44
starting at the column address output by the address register
12
. In either case, the column address buffer
44
applies a column address to a column decoder
48
, which applies various column signals to respective sense amplifiers and associated column circuits
50
and
52
for the respective arrays
20
,
22
.
Data to be read from one of the arrays
20
,
22
are coupled from the arrays
20
,
22
, respectively, to a data bus
58
through the column circuit
50
or
52
, respectively, and a read data path that includes a data output register
56
. Data to be written to one of the arrays
20
,
22
are coupled from the data bus
58
through a write data path, including a data input register
60
, to one of the column circuits
50
,
52
where they are transferred to one of the arrays
20
,
22
, respectively. A mask register
64
may be used to selectively alter the flow of data written to the arrays
20
,
22
.
The above-described operation of the SDRAM
10
is controlled by a control logic circuit
66
which includes a command decode circuit
68
and a mode register
69
. The control logic circuit
66
is responsive to high level command signals received from a control bus
70
through the command decode circuit
68
. The high level command signals, which are typically generated by the memory controller, are a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*. The memory controller also typically provides a clock enable signal CKE* and a clock signal CLK through the control bus
70
to the control logic circuit
66
. The “*” designates the signal as active low. The control logic circuit
66
generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. The command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of the command signals will be omitted.
At the beginning of its operation, the SDRAM
10
is supplied with an operating voltage Vcc, which rises from 0 volts to about 3 volts, and the SDRAM
10
undergoes a power up procedure, also called a boot up procedure, to initialize it for operation. As Vcc is rising, the control logic circuit
66
generates a power up pulse which is a single pulse having a duration defined between a leading edge and a trailing edge. The power up pulse may be generated by an RC circuit. The power up pulse may also be generated by a level translator based on the rising Vcc, or by a combination of a level translator and an RC circuit. The power up pulse is applied to override most circuitry in the SDRAM
10
to place the circuitry in a known state.
The control logic circuit
66
includes a substantial number of antifuse circuits in several antifuse banks
90
located between the address latches
26
,
40
, and the respective decoders
28
,
48
. The antifuse circuits in the antifuse banks
90
are used to identify defective rows or columns in the SDRAM
10
. The antifuse circuits are arranged in groups of
8
, and each group may be programmed to provide an address of a defective row or column. Once programmed, each antifuse circuit must be read or strobed by a read signal before it can provide a digital value in an address. The read signal is a single pulse with a duration that must be long enough to properly read each antifuse circuit. During the boot up procedure the read signal is generated in the control logic circuit
66
in response to the power up pulse, and its duration is approximately equal to the duration of the power up pulse.
The SDRAM
10
also includes a large number of registers
92
that are programmed with data during its operation to define modes of operation for each element in the SDRAM
10
. The registers
92
include an input mode register, an output mode register, a register for the output buffers, and a register for initializing the control logic circuit
66
. These and many more registers
92
are located across the SDRAM
10
as needed. The registers
92
are made up of latches that are in an unknown state prior to the boot up procedure and are initialized or put into a known state by the power up pulse before the SDRAM
10
begins operating. The initialization of the registers
92
prevents elements in the SDRAM
10
from behaving in an uncontrolled manner. For example, the register for an output buffer indicates when data is to be driven onto a bus and when the output buffer is to be tri-stated. If the output buffer was allowed to drive data onto the bus in a random fashion a conflict over buses in the SDRAM
10
would occur, leading to bus contention and possibly other problems.
A proper operation of the SDRAM
10
depends on the duration of the power up pulse. If there is a spike in the rising Vcc or Vcc is not generated with the appropriate power ramp rate, the power up pulse will not be long enough to support a reading of the antifuse circuits or to initialize the registers
92
. In addition, logic in the SDRAM
10
will not operate when Vcc is below about 1.5 volts, or below 50% of a steady Vcc. In either case, the antifuse circuits may not be read correctly and the registers
92
may not be initialized if the power up pulse is too short, with the result that the SDRAM
10
will not operate properly.
The SDRAM
10
is also initialized during a reboot procedure of a computer including the SDRAM
10
. The reboot procedure, also called a hot boot procedure, reinitializes the computer at the direction of a user while Vcc is maintained at a stable level and not interrupted and no power-up pulse is generated. Without the power-up pulse, the registers
92
are not reinitialized and the antifuse circuits are not read in the reboot procedure. The SDRAM
10
may start operating in an undefined mode after the reboot procedure because the registers
92
retain data which may conflict with instructions received during the reboot procedure.
SUMMARY OF THE INVENTION
I
Beausoliel, Jr. Robert W.
Crockett Robert G.
Dorsey & Whitney LLP
Micron Technology. Inc.
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