Method and apparatus for initial state extraction

Details Method and apparatus for initial state extraction Method and apparatus for initial state extraction

2007-08-21

2007-08-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11149827

ABSTRACT:
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFGand HLMDFG. RTLMDFGand HLMDFGare then put into timestep form and are called RTLMtsand HLMts. A test bench CStsis selected that couples RTLMtsand HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. The user specifies a location within the HLM where initialization is finished. The HLM is executed, with procedure calls related to memory allocation intercepted and allocation information collected. The initialization techniques can be used with any formal analysis tool operating on representations derived from an HLM.

REFERENCES:
patent: 6467075 (2002-10-01), Sato et al.
patent: 6937973 (2005-08-01), Panesar
patent: 7007264 (2006-02-01), Baxter
patent: 2002/0019969 (2002-02-01), Hellestrand et al.

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