Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-07-20
2003-12-09
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S024000, C710S302000
Reexamination Certificate
active
06662320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved handling of reset operations and, in particular, to a method and an apparatus for managing error signals. Still more particularly, the present invention provides a method and an apparatus for inhibiting the generation of spurious error signal following the reset of an adapter card or bridge circuit.
2. Description of the Related Art
In a typical computer system, interrupts are handled via a host bridge between the devices plugged into card slots on the system bus and the interrupt processing hardware and software. For example, in a PCI (Peripheral Component Interconnect) system commonly used for personal computers and workstations, there is a PCI Host Bridge (PHB).
The adapter chips or bridges in a system can be reset due to a variety of hardware or software conditions. For example, in many systems the devices are “hot plugable”, which means devices can be added or removed from the system while other parts of the computer are fully functional. This leads to difficulties since the component coming out of reset is not synchronized with the rest of the system and may become active when another adapter is in the middle of a transaction.
Consider the case of parity error checking. Parity is based on a sequence of data and is only accurate if the entire sequence is processed. If an adapter comes out of reset when a data sequence from another adapter using the same system bus is partially completed, then the adapter coming out of reset will most likely detect a parity error since it has not seen the entire sequence of data. Most likely this will be a spurious error signal where no real error existed. This results in an error report that cannot be explained when the data is examined and appears to be “good.”Therefore, it would be advantageous to have a method and an apparatus that prevents an adapter that has been reset from issuing spurious error signals due to the fact it was not synchronized with the system at the time it came out of reset.
SUMMARY OF THE INVENTION
A method and an apparatus is presented for preventing an adapter card that has been reset from issuing spurious error signals due to the fact it is not synchronized with the system at the time it comes out of reset. For example, if an adapter card comes out of reset when another adapter card on the same system bus is sending a parity sensitive data stream, then the adapter coming out of reset will most likely detect a parity error since it has not seen the entire sequence of data. This is a spurious error signal where no real error exists.
To prevent spurious errors, the data processing issues a command to the adapter card that is to be reset that disables error checking before the reset command is sent. The reset command is sent next. After the adapter card completes the reset operation, it notifies the system that the reset is completed. The adapter card waits until it receives a command from the system to re-enable error checking before it turns back on error checking. In this manner, the system can insure that error checking is only turned back on synchronously with other system activities so that spurious error signals are not generated.
REFERENCES:
patent: 5448725 (1995-09-01), Gervais
patent: 5815647 (1998-09-01), Buckland et al.
patent: 5864656 (1999-01-01), Park
patent: 6061810 (2000-05-01), Potter
patent: 6247144 (2001-06-01), Macias-Garza et al.
patent: 6253320 (2001-06-01), Sekiguchi et al.
patent: 6370657 (2002-04-01), Jansen et al.
Cabezas Rafael Graniello
Kovacs Robert George
Perez Michael Anthony
Baderman Scott
Lohn Joshua
McBurney Mark E.
Yee Duke W.
Yociss Lisa L. B.
LandOfFree
Method and apparatus for inhibiting an adapter bus error... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for inhibiting an adapter bus error..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for inhibiting an adapter bus error... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3132281