Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-03-21
1995-12-12
Clawson, Jr., Joseph E.
Static information storage and retrieval
Read/write circuit
Bad bit
36518905, 365195, 36523003, 36523006, 371 103, G11C 800
Patent
active
054756405
ABSTRACT:
A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).
REFERENCES:
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4791615 (1988-12-01), Pelly et al.
Kersh, III David V.
Norwood Roger D.
Clawson Jr. Joseph E.
Donaldson Richard L.
Kesterson James C.
Nerrings Ronald O.
Texas Instruments Incorporated
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