Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-04
2008-03-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07340702
ABSTRACT:
Inductive proof can be an improvement to bounded verification. Forward and backward inductive proof methods are disclosed, which can improve the process of verifying properties of circuit designs. An inductive set of one or more states includes passing a first property of a circuit design. State of the inductive set passing at least the first property of the circuit design are transitioning by at least one step in a forward direction, resulting in transitioned states. It is determined if the transitioned states of the inductive set pass at least the first property of the circuit design. At least the transitioning and the determining are repeated, until at least, the determining results in the transitioned states of the inductive set passing at least the first property of the circuit design.
REFERENCES:
patent: 5331568 (1994-07-01), Pixley
patent: 6163876 (2000-12-01), Ashar et al.
patent: 6484134 (2002-11-01), Hoskote
patent: 6745160 (2004-06-01), Ashar et al.
patent: 2002/0178424 (2002-11-01), Gupta et al.
patent: 2004/0153308 (2004-08-01), McMillan et al.
patent: 2004/0230407 (2004-11-01), Gupta et al.
Sheeran et al., “Checking Safety Properties Using Induction and a SAT-Solver”, Nov. 2000, In Proc. Conference on Formal Methods in Computer-Aided Design.
Wedler et al., “Using RTL statespace information and state encoding for induction based property checking”, 2003, Design, Automation and Test in Europe Conference and Exhibition, pp. 1156-1157.
Wedler et al., “Exploiting state encoding for invariant generation in induction-based property checking”, Jan. 27-30, 2004, Desi Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific, pp. 424-429.
Shende et al., “Synthesis of reversible logic circuits”, Jun. 2003, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, Issue: 6, pp. 710-722.
Prakash et al., “A high-performance architecture and BDD-based synthesis methodology for packet classification”, Jun. 2003, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, Issue: 6, pp. 698-709.
Parthasarathy et al., “Safety property verification using sequential SAT and bounded model checking”, Mar.-Apr. 2004, Design & Test of Computers, IEEE, vol. 21, Issue 2, pp. 132-143.
De Moura et al., “Bounded model checking and induction: from refutation to verification”, 2003, In: Proceedings of Computer-aided verification, CAV, pp. 14-26.
Awedh et al., “Proving more properties with bounded model checking”, 2004, 16th International Conference, CAV 2004, vol. 3114, pp. 96-108.
International Search Report and Written Opinion for PCT/US03/23637 dated May 16, 2005.
International Search Report and Written Opinion for PCT/US04/23637 dated May 16, 2005.
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Chiang Jack
Rossoshek Helen
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