Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-03
2002-12-10
Thomas, Tom (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06493851
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to simulation tools for predicting the performance of integrated circuit components. In particular, the present invention relates to improving the correlation between the predicted performance for the components and the measured performance for the components.
Integrated circuits are produced by sequentially depositing layers of material on a substrate. Before an integrated circuit can be produced, a large number of masks must be designed that will define the locations for the various material layers. The design and production of these masks represents a significant fixed cost in the production of integrated circuits. As such, it is desirable to ensure that the integrated circuit will operate properly before the masks are produced.
This is typically done by simulating the performance of the individual components of the integrated circuit using a collection of modeling tools. These modeling tools include transistor models, which are used in transistor level simulators, such as HSPICE. They also include cell level models that describe the performance of basic building blocks of logic called standard cells. In particular, the cell models provide timing models describe the propagation delay through the standard cell. During simulations, the propagation delays through the various cells are taken into consideration when performing chip-level timing analysis.
As device sizes become smaller and the speed of devices increase, even small errors in the simulation models significantly reduce the correlation between the performance predicted by the simulation model and the actual performance of the circuit. In the worst case, a circuit will appear to operate properly in simulation, but will not operate at all when it is built.
In the past, testing was done to determine if a component performed as predicted. If the testing showed that the component performance met expectations, the model for the component was accepted as being accurate. However, if the component did not perform as expected, the testing indicated that the model was inaccurate. One problem with this testing was that it did not show why the model did not correlate with the built component. In other words, prior art testing did not indicate the cause of poor correlation between the model and the built component.
SUMMARY OF THE INVENTION
A method identifies the cause of poor correlation between an integrated circuit model and measured integrated circuit performance. The method includes determining the propagation delays through two separate integrated circuit components. The propagation delays are then compared to each other to identify the cause of the poor correlation.
REFERENCES:
patent: 6216099 (2001-04-01), Fang et al.
patent: 6216256 (2001-04-01), Inoue et al.
Bach Randall E.
Davis Robert W.
LSI Logic Corporation
Owens Douglas W.
Thomas Tom
Westman Champlin & Kelly
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