Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-11
2010-12-28
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07861199
ABSTRACT:
In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slack for the circuit, determining a slack of at least one diagnostic entity, and computing a diagnostic metric relating to the diagnostic entity(ies) from the chip slack and the slack of the diagnostic entity(ies).
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Visweswariah Chandramouli
Xiong Jinjun
Zolotov Vladimir
Garbowski Leigh Marie
International Business Machines - Corporation
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