Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-06-09
2001-07-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S189050, C365S189070
Reexamination Certificate
active
06256248
ABSTRACT:
FIELD OF THE INVENTION
The present invention is applicable to semiconductor memories that must be periodically refreshed, such as dynamic random access memory (DRAM). More specifically, the present invention relates to a structure and method for increasing the amount of time available for performing internal refresh operations within a memory by performing refresh operations during burst access operations.
DISCUSSION OF RELATED ART
Many prior art memory systems use read and write buffers in connection with RAM arrays. One such memory system is described in U.S. patent application Ser. No. 08/679,873, entitled “Method and Structure For Performing Pipeline Burst Accesses In a Semiconductor Memory”, by Wingyu Leung. This memory system uses read and write buffers to enable the bit lines and sense amplifications in the RAM array to begin pre-charging before a burst read or write transaction is finished. The early pre-charge operation prepares the RAM array for the next transaction and thereby reduces the access time of the memory system.
Another memory system using read and write buffers in connection with a RAM array is described in U.S. patent application Ser. No. 08/812,000, entitled “Method and Structure for Implementing a Cache Memory Using A DRAM Array”, by Wingyu Leung. This memory system uses read and write buffers to bridge the bandwidth and transfer discrepancy between a RAM array and an external system accessing the memory system.
In both of the memory systems described above, the RAM array is not refreshed in parallel with the transfer of data to and from the RAM array.
Other conventional memory systems use a cache memory in connection with a DRAM array. One such memory system is described by K. Dosaka, et. al in “A 100 MHz 4 mb Cache DRAM with Fast Copy-Back Scheme”, Digest of ISSCC, pp. 148-149 (1992). In this memory system, a small SRAM cache having a relatively short access time is used in connection with a main DRAM array. The SRAM cache is controlled to reduce the average access time of the memory system. The SRAM cache is not used to allow more time for internal memory refresh operations. The access time of the memory system varies depending on the hit rate of the SRAM cache. In addition, this memory system requires external control for memory refresh operations.
Another conventional memory system is described in “131,072-Word by 8-Bit CMOS Pseudo Static RAM”, Toshiba Integrated Circuit Technical Data (1996). This memory system attempts to use a DRAM array for SRAM applications. However, the DRAM array must be periodically refreshed. In this memory system, the DRAM array cannot be refreshed during an external access, because the DRAM array is busy. This memory system requires an external signal for controlling the refresh of the DRAM array. External accesses are delayed during refresh operations. As a result, the refresh operations are not transparent and the memory system cannot be fully compatible with an SRAM device.
Another conventional memory system is described by K. Ayukawa, et. al, in “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's”, IEEE JSSC, vol. 33, no. 5, May 1998. This memory system uses a write buffer to speed up the write access in an embedded DRAM. In this memory system the DRAM cycle time takes multiple clock periods and there is no mention of performing refresh operations in parallel with I/O data transfer to an external device.
It would therefore be desirable to have a memory system that controls the operation of a DRAM array in a manner that provides additional time for the DRAM array to be refreshed.
SUMMARY
The present invention therefore provides a memory system that includes a DRAM array, a read buffer, a write buffer and an input/output (I/O) interface. The read buffer and write buffer are coupled between the DRAM array and the I/O interface. When an external transaction involves multiple pieces of data in consecutive address locations, such as a burst access, parallel operations are performed in the DRAM array and the I/O interface.
In a burst read transaction, all the data in the burst transaction is pre-fetched from the DRAM memory into the read buffer in one memory cycle. After the read data has been pre-fetched, the DRAM array is available for a refresh operation. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/O interface. In one example, four data words are pre-fetched from the DRAM array to the read buffer during a first memory cycle. One of these four data words is transferred to the I/O interface during this first memory cycle, and the other three data words are sequentially transferred to the I/O interface during the next three memory cycles. Because the DRAM array is not engaged in the transfer of data values from the read buffer to the I/O interface, the DRAM array can be refreshed during these next three memory cycles.
In a burst write transaction, multiple burst write data values are written to the write buffer over multiple I/O cycles. This burst write data is not retired to the DRAM array until the next write transaction. At this time, all of the burst write data is simultaneously retired to the DRAM array. In one example, four data words are written to the write buffer over four I/O cycles during a first write burst transaction. During a second write burst transaction, these four data words are simultaneously retired to the DRAM array during a first I/O cycle. Also during the second write burst transaction, four new data words are written to the write buffer over four I/O cycles. As a result, the DRAM array is only engaged in the burst write transaction for one memory cycle. Because the DRAM array is not engaged in the transfer of the new data values from the I/O interface to the write buffer, the DRAM array can be refreshed during one or more of the remaining three I/O cycles.
Because the read and write buffers are controlled to limit the time that the DRAM array is engaged in a burst read or burst write transaction to one memory cycle, the available time for refreshing the DRAM array is maximized. Moreover, reducing the time that the DRAM array is engaged in read and write transactions significantly reduces the operating power of the memory system, since most of the power is consumed by the operation of the DRAM array.
The present invention also includes a comparator that is coupled to receive a current access address and an address associated with the data stored in the write buffer. Upon detecting a match between these two addresses, the comparator asserts a HIT control signal. If the current access is a read transaction, the asserted HIT control signal indicates that data required by the read transaction is stored in the write buffer, and has not yet been retired to the DRAM array. Under these conditions, write buffer control circuitry accesses the write buffer to retrieve the data required by the read transaction, thereby ensuring that coherent data is provided during the read transaction. In one embodiment, data from the write buffer and data from the DRAM array is merged onto an internal data bus using a maskable write driver circuit.
The present invention will be more fully understood in view of the following description and drawings.
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Bever Hoffman & Harms LLP
Hoang Huan
Hoffman E. Eric
Monolithic System Technology, Inc.
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