Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-03-30
2002-10-15
Tran, M. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S230010
Reexamination Certificate
active
06466473
ABSTRACT:
BACKGROUND
This invention is generally related to solid state memory arrays in which the memory elements have a polarizable material such as a dipole ferroelectric material, and more particularly related to reading stored information from such arrays with increased signal to sneak ratio.
Applications of cross-point solid state memory arrays with polarizable materials include non-volatile cache memory inside a hard disk drive and perhaps even a replacement to the hard disk drive. That's because such memory arrays provide very high density storage of binary information and fast access speeds. In such devices, binary information (a combination of “1”s and “0”s) may be stored in an array of polarizable memory elements, where each element has at least two possible states that represent one bit (“1” or “0”) of stored information. In a switched dipole memory array, each element has a dipole that can retain a written electric or magnetic state after power has been turned off. These non-volatile elements retain the written state until rewritten by an externally imposed electric or magnetic field that switches the state of the element.
The voltage vs. charge behavior of a dipole element, as measured across a pair of the element's terminals, exhibits hysteresis as shown in FIG.
1
. The hysteresis allows the element to exhibit any one of two different states of charge (labeled A and B) when the voltage is at a ‘static’ level, here zero volts, depending upon the last write operation. To write A, the terminal voltage is increased above an upper polarization voltage, Vh; this causes the resulting state to either remain at A or change from B to A. Conversely, to write B, the terminal voltage is decreased below a lower polarization voltage Vl; this causes the resulting state to either remain at B or change from A to B. The state is retained by keeping the terminal voltage at the static level. Note that some variation in the terminal voltage around the static level may be tolerated without changing the state of the element. This variation in terminal voltage is sometimes called a ‘half-read’.
To actually read an existing state of an element, the following procedure may be performed. First, B is written to the element. If a charge is released (either positive or negative), which signifies that the write resulted in a change of state, then the preexisting state must have been A. On the other hand, if no essentially no charge is released, which signifies that the write did not cause a change of state, then the preexisting state must have been B. Of course, if the preexisting state was A, then the state should be changed back to A following the write of B.
To access the elements for reading and writing, a cross-point matrix of conductive lines is formed around the elements, where each element
202
(i,j) is associated with a respective crossing of a pair of vertical and horizontal lines, as seen in FIG.
2
. The vertical lines
204
_
1
,
204
_
2
, . . .
204
_N (
204
) in this example are known as bitlines, while the horizontal lines
208
_
1
,
208
_
2
, . . .
208
_M (
208
) are called wordlines. To read element(
1
,
1
), the voltage between wordline
1
and bitline
1
needs to be changed from its static level to the polarization level, and then the charge released on bitline
1
by element (
1
,
1
), known as a ‘signal’ charge, needs to be measured.
A problem, however, with measuring an addressed element's signal charge is that since all other elements in the same column as the addressed element are electrically connected to the same bitline, there is a significant ‘sneak’ charge that is released by the other elements while attempting to read the addressed element. This sneak charge can be orders of magnitude larger than the signal charge when the memory array is large.
Typically, an element access operation has two phases. During a bitline settling phase, the addressed bitline, the addressed wordline, and all other wordlines of the array (these are referred to as being ‘unaddressed’) are forced to intermediate voltages (less than the polarization voltage) which cause an amount of sneak charge to be released. In a subsequent signal integration phase, the addressed bitline and wordline are driven to the polarization voltage which causes an amount of signal charge (typically much smaller than the total amount of sneak charge) to be released and integrated. There are two limited solutions that allow the signal to be distinguished from the sneak. In the first case, the bitline settling phase is extended to allow a change in the bitline current, which is essentially caused by induced sneak charge during this phase, to dissipate prior to starting integration of the bitline current. Upon halting integration, this yields a value for total bitline charge including the signal charge. A value representing an estimate of the amount of sneak charge only (without any signal charge contribution) is then subtracted from the total bitline charge, to obtain a net bitline charge which represents only the signal charge induced during the integration interval. In the second solution, the integration phase is extended to allow more signal charge to contribute to the total bitline charge. Although both of these solutions attempt to increase the measured signal to sneak ratio in the integration phase, they lead to increased delays in accessing an element in the memory array which severely restricts the access speed.
REFERENCES:
patent: 5363325 (1994-11-01), Sunouchi et al.
patent: 5400275 (1995-03-01), Abe et al.
patent: 5615144 (1997-03-01), Kimura et al.
patent: 6147896 (2000-11-01), Kim et al.
patent: 0183092 (1987-08-01), None
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndedition, pp. 654-655.
Chow David G.
Nair Rajendran
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