Method and apparatus for increasing processor performance

Details Method and apparatus for increasing processor performance Method and apparatus for increasing processor performance

1996-07-08

1998-09-01

Pan, Daniel H.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395391, 395570, G06F 930, G06F 1202, G06F 1338

Patent

active

058025642

ABSTRACT:
A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

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