Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-06-30
2002-12-31
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S027000, C710S038000
Reexamination Certificate
active
06502159
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to computer systems, and more specifically to techniques for increasing data throughput in such systems.
In conventional systems, data transfers are generally under the control of the CPU, and data flow can be between the CPU and system memory, between the CPU and persistent data storage devices, between the data storage devices and the system memory, and between the CPU and peripheral devices. In addition to requiring CPU cycles, such data transfers also occupy the buses that connect the various devices. As the power of CPUs has increased, the data flow needs in the computer system also have increased. In general, however, the techniques for efficiently moving data among the various devices in the system have not kept pace with the huge increases in CPU power.
In modern multitasking operating systems, the computer system executes different programs concurrently. However, with many different processes competing both for CPU resources and bus bandwidth, any bottlenecks have the effect of slowing the entire system. These problems are especially evident in modern computers which include multimedia capabilities. In recognition of the fact that there is in general a mismatch in the relative speeds and demands of various devices in the system, multiple-level bus systems have been developed.
FIG. 1
shows a schematic of a conventional personal computer system
10
utilizing a three-bus system in which a CPU
12
communicates with other system resources. The buses are arranged in a hierarchy based on speed and width. In a typical PC-compatible system, the CPU communicates with a memory subsystem and various I/O (peripheral) devices. The nature of these devices is well known, but will be described briefly.
The CPU communicates with a memory subsystem (including system memory
15
and second-level cache memory
17
) on a system bus
20
, also referred to as a host bus or a local bus, while one or more.peripheral buses are used for other devices. In a modern system, the system bus is a 64-bit bus that operates at 66 MHz.
In the specific architecture shown in
FIG. 1
, the peripherals are coupled to one or the other of a fast peripheral bus
25
, such as a PCI bus, or a slow peripheral bus
30
. The slow peripheral bus is typically an industry standard expansion bus such as an ISA bus, an EISA bus, or an MCA bus. The industry standard expansion bus is often referred to herein as a legacy bus, since its primary purpose is to be compatible with past generations of 8-bit and 16-bit peripheral devices whose functions are such that they can still perform adequately in a modern system. In particular, the PCI bus is coupled to the system bus through a host/PCI bridge
32
, while the PCI bus is coupled to the legacy bus through a PCI/legacy bridge
35
. In an alternative configuration, the legacy bus is coupled to the system bus through a host/legacy bridge
37
. This latter configuration is suggested by having host/legacy bridge
37
shown in phantom. In a typical implementation, host/PCI bridge
32
is part of a chipset that also incorporates system logic such as a memory controller for system memory
15
.
As a general matter, the PCI bus includes PCI bus resources (a PCI bus master, PCI target memory, and PCI target I/O), while the legacy bus includes legacy bus resources (a legacy bus master, legacy memory, and legacy I/O). The choice of which peripherals go on which bus is determined in part by cost and speed considerations. In general, PCI bus peripherals are faster and wider versions of the same types of peripherals that can be coupled to the legacy bus. For example, PCI bus
25
is a 32-bit bus that operates at 33 MHz while an ISA bus is a 16-bit bus that operates at 8 MHz.
In the specific embodiment illustrated, the devices coupled to PCI bus
25
include a display controller
40
, such as a VGA controller or super VGA controller, and an enhanced IDE controller
45
. There are a number of interface standards for peripherals, the most common of which are IDE (Integrated Device Electronics) and SCSI (Small Computer System Interface). These interfaces receive commands from the CPU, and control the operation of the connected peripheral devices. An IDE interface controller, such as a Model M
5215
chip from Acer Laboratories, controls up to two disk drives at once. The enhanced IDE interface standard provides for faster data transfers and controls up to four disk drives at once.
Enhanced IDE interface controller
45
includes primary and secondary IDE interface controllers, and in this embodiment communicates with a hard disk drive
47
and a CD-ROM drive
48
.
The legacy bus devices include a super I/O controller
50
, which is interfaced to a floppy disk drive
52
, and an MPEG card
57
, which is interfaced to a display device
60
such as a CRT monitor or the like. Also coupled to the legacy bus are peripherals such as a network interface card
65
(which may be an Ethernet® card) and a sound card
67
. Also shown schematically connected to legacy bus
30
are a ROM BIOS
75
, a printer
77
, a keyboard
80
, a pointing device
82
(which may be a mouse, trackball, or similar device), and a scanner
85
. It should be understood that coupling of some of these latter devices is shown schematically since they may be coupled to alternative ports and derived buses.
Display controller
40
is coupled to MPEG card
57
by a feature connector
90
in order that the display controller and MPEG controller can coordinate to drive the display. The feature connector is a cable that provides signals, including the DAC signals, to the MPEG card. In other embodiments control signals could be communicated over the bus.
Consider a conventional technique for displaying data stored on a CD in CD-ROM drive
48
on display device
60
. The following sequence of steps illustrate the process:
1. CPU
12
executes the CD-ROM driver and MPEG driver programs, which both reside in system memory
15
.
2. CPU
12
issues a PLAY command to enhanced IDE controller
45
.
3. In response to the PLAY command issued by CPU
12
, enhanced IDE controller
45
issues a corresponding PLAY command to CD-ROM controller
48
.
4. In response to the PLAY command, CD-ROM controller
48
reads CD-ROM data into its CD-ROM controller buffer.
5. Enhanced IDE controller
45
reads data from the CD-ROM controller buffer into its enhanced IDE controller buffer.
6. Host/PCI bridge
32
reads the data from the enhanced IDE controller buffer into its Host/PCI bridge buffer via PCI bus
7
.
7. Host/PCI bridge
32
reads data from the Host/PCI bridge buffer and transfers it to CPU
12
via system bus
20
.
8. Host/PCI bridge
32
reads data from CPU
12
into system memory
15
via system bus
20
.
9. Host/PCI bridge
32
reads data from system memory
15
into CPU
12
via system bus
20
.
10. Host/PCI bridge
32
reads data from CPU
12
into the Host/PCI bridge buffer via system bus
20
.
11. Host/PCI bridge
32
reads data from the Host/PCI bridge buffer and transfers it to the PCI/Legacy bridge's buffer via PCI bus
25
.
12. PCI/Legacy bridge
35
transfers data from the PCI/Legacy bridge buffer into the MPEG card's buffer via legacy bus
30
.
13. MPEG card
57
decompresses the data and outputs accordingly to display device
60
, incorporating the signals from display controller
40
.
The data flow is shown schematically in Table 1.
While this type of data transfer may not present a major problem for some types of data, consider the case where the CD-ROM is used for playing a movie clip. The large amount of data to be processed and transferred represents a major load on the system. For example, for a 320×200 24-bit color picture, the size is about 187.5 KB (320*200*24÷8) for but a single frame. A movie needs to play
30
frames per second, which would result in a file of size 5.5 MB for one second's playing, or 330 MB for one minute's playing, or 30 GB for 90 minutes' playing. If high fidelity is required, the data size will even incre
Chuang Te-Chih
Hsu Hsi-Yuan
Huang Hsueh-Wei
Acer Incorporated
Dharia Rupal
Slone David N.
Townsend and Townsend / and Crew LLP
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