Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
1999-09-08
2002-06-11
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C713S001000, C713S100000, C370S256000
Reexamination Certificate
active
06405270
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to data transmission, and more particularly to a method and apparatus for altering the topology of a serial bus in order to increase data rates between nodes of the serial bus.
The IEEE 1394 standard defines a high performance serial bus cable environment that includes a network of nodes connected by point-to-point links called physical connections. A physical connection consist of a port on each of two nodes and a cable between the ports of the two nodes. A node can have multiple ports which enables a branching multi-hop interconnection between nodes. The fixed round-trip time of the arbitration protocol limits the multi-hop interconnections between nodes. In an environment uses inexpensive interconnect cables having 28-gauge signal pairs, the default timing after a bus reset is adequate for 16 cable hops that are each 4.5 meters in length for a maximum distance between nodes of the 1394 serial bus of 72 meters.
Whenever a node is added to or removed from the 1394 serial bus, a bus reset occurs that forces all nodes to a known state. After a bus reset, a tree identify (ID) process translates the general network topology into a tree, where one node is designated a root and all of the physical connections are labeled as either a parent, a child, or as unconnected. Any unconnected ports are labeled as off and do not participate any further. The tree must be acyclic (i.e. no loops allowed); otherwise, the tree ID process will not be completed.
The 1394 environment supports multiple data rates of approximately 98.304, 196.61, 393.22, 786.43, 1,572.9, and 3,145.7 megabits per second which are commonly referred to as S100, S200, S400, S800, S1600, and S3200, respectively. The lowest speed, S100, is also known as the base rate, and all ports that support a higher data rate must also support the lower base rate. Nodes capable of data rates greater than the base rate exchange speed information with the other nodes through the attached ports during a speed signaling phase of normal bus arbitration. If a peer node is incapable of receiving data at a higher data rate, then the node will not propagated data received at the higher data rate down that path. In other words, nodes will only propagate high speed data down paths that support the higher data rate.
During data packet transmission, the source node sends a speed code, format and transaction codes, addresses of the source and destination nodes, and data. The destination field in the packet is used by the link layer of each node to determine if the corresponding node is the recipient of the transmitted data. The maximum speed at which a data packet can be transmitted depends upon the maximum supported speeds of the transmitting and receiving nodes as well as the maximum supported speeds of any nodes connected between the transmitting and receiving nodes. In particular, the maximum speed for data transmission is equal to the highest speed that is supported by the sending node, receiving node, and all the nodes connected between the sending node and the receiving node.
Since the maximum speed at which a data packet can be transmitted depends upon nodes connected between the sending node and the receiving node, the overall performance of the serial bus is dependent upon the topology of the serial bus. In other words, altering the manner by which nodes of the serial bus are interconnected via the physical connections may improve the overall performance of the serial bus if slower nodes connected between faster nodes are moved such the slower nodes are not connected between faster nodes. The problem is that typical computer users do not appreciate that the manner by which the nodes of the serial bus are interconnected effects the overall performance of the serial bus. Moreover, even if computer users appreciated this fact, typical computer users do not know how to obtain the maximum data rate supported by each node of their serial bus nor how to utilize the maximum data rate information to configure the serial bus for increased performance.
Accordingly, a need exists for a method and apparatus that increase overall bus performance of a serial bus by optimizing the manner by which nodes of the serial bus are interconnected.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided a method of altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between said plurality of nodes. One step of the method includes obtain a current topology representation of said serial bus which indicates a first node of said plurality of nodes is coupled to a second node of said plurality of nodes via a third node of said plurality of nodes. Another step of the method includes obtaining data rate capabilities of each node of said serial bus. The method also includes the step of determining based upon said current topology representation of said serial bus and said data rate capabilities of each node that said third node of supports a third maximum data rate that is slower than a first maximum data rate supported by said first node and a second maximum data rate supported by said second node. Furthermore, the method includes the step of generating in response to the determining step a new topology representation for said serial bus in which said third node is not coupled between said first node and said second node.
Pursuant to another embodiment of the present invention, there is provided a system for altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between the plurality of nodes. The system includes a processor, a serial bus adapter operable to provide the processor with an interface to the plurality of nodes, and a memory comprising a plurality of instructions. The plurality of instructions when executed by the processor cause the processor to obtain a current topology representation of the serial bus via the serial bus adapter which indicates a first node of the plurality of nodes is coupled to a second node of the plurality of nodes via a third node of the plurality of nodes. Furthermore, the plurality of instructions when executed by the processor cause the processor to obtain data rate capabilities of each node of the serial bus via the serial bus adapter. Moreover, the plurality of instructions when executed by the processor cause the processor to generate a new topology representation for the serial bus in which the third node is not coupled between the first node and the second node in response to determining based upon the current topology representation of the serial bus and the data rate capabilities of each node that the third node supports a third maximum data rate that is slower than a first maximum data rate supported by the first node and a second maximum data rate supported by the second node.
Pursuant to another embodiment of the present invention, there is provided a computer readable medium for configuring a system for altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between the plurality of nodes. The computer readable medium includes a plurality of instructions which when executed by the system cause the system to obtain a current topology representation of the serial bus which indicates a first node of the plurality of nodes is coupled to the second node of the plurality of nodes via a third node of the plurality of nodes. The plurality of instructions when executed by the system also cause the system to obtain data rate capabilities of each node of the serial bus. Moreover, the plurality of instructions when executed by the system further cause the system to generate a new topology representation for the serial bus in which the third node is not coupled between the first node and the second node in response to determining based upon the current topology representation and the data rate capabilitie
LSI Logic Corporation
Maginot Moore & Bowman
Thai Xuan M.
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