Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-11
2001-12-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C326S037000
Reexamination Certificate
active
06334208
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to programmable logic devices (PLDs) and in particular to a method and apparatus for programming programmable logic devices.
2. Description of the Related Art
Programmable logic devices (PLDs) are a class of integrated circuits which can be programmed by a user to implement user defined logic functions. PLDs, long known in the art, are often used in electronic systems because, unlike custom “hard-wired” logic circuits or application specific integrated circuits (ASICs), PLDs can be programmed and reprogrammed quickly to incorporate modifications to the implemented logic functions.
One major class of PLDs are referred to as programmable logic array (PLA) devices or programmable array logic (PAL) devices. Basically, these early PLDs include an AND plane which logically ANDs two or more input signals to produce product terms (P-terms), and an OR plane which logically ORs two or more of the P-terms generated by the AND plane. (“Plane” here generally refers to a grouping of logic gates and not to a geometric plane.) The AND plane is typically a matrix of programmable connections where each column connects to an input pin of the PLD, and each row forms a P-term which is transmitted to the OR plane. The OR plane may be programmable (i.e., each P-term is programmably connectable to one of several different OR plane outputs), in which case the PLD is referred to as a PLA device. Alternatively, the OR plane may be fixed (i.e., each P-term is assigned to a particular OR plane output), in which case the PLD is referred to as a PAL device. The AND plane and OR plane of PLA and PAL devices implement logic functions represented in the sum-of-products form.
PLA and PAL devices were well-received by logic designers when their implemented logic functions were relatively small. However, as logic functions grew increasingly larger and more complex, logic designers were required to wire together two or more small PLDs to provide sufficient logic capacity. Although this process was tolerated during development and testing, it increased the cost and size of production units. This generated a demand for PLDs with increasingly larger logic capacity.
To meet the ever-increasing demand for greater capacity, PLDs with increasingly complex architectures have been developed. One popular complex PLD type, known as complex programmable logic devices (CPLDs), includes two or more function blocks connected together and to input/output (I/O) modules by an interconnect matrix such that each of the function blocks selectively communicates with the I/O modules and with other function blocks of the CPLD through the interconnect matrix. External pins on the device connected to the I/O modules are also referred to as functional pins.
Each function block of the CPLD is structured like the two-level PLDs, described above. In effect, CPLDs incorporate several early PLDs and associated connection circuitry onto a single integrated circuit. This provides a circuit designer the convenience of implementing a complex logic function using a single IC.
Each function block of an early CPLD typically includes an AND array and a set of macrocells. The AND array includes a set of input lines for receiving input signals from the interconnect matrix, and a set of product term (P-term) lines for transmitting P-term signals to the macrocells. Each P-term line is connected to the input lines using programmable connections which allow logic ANDing of two or more of the input signals. Each macrocell includes an OR gate which is programmable to receive one or more of the P-term signals transmitted on the P-term lines. The OR gate of each macrocell produces a sum-of-products term which is either transmitted to the I/O modules of the CPLD, fed back through the interconnect matrix, or is transmitted on special lines to an adjacent macrocell.
Some CPLDS, such as XC7300 series CPLDs and XC9500 series CPLDs produced by Xilinx, Inc. of San Jose, Calif., incorporate “cross-point” interconnect matrices. Cross-point interconnect matrices include a plurality of parallel word (input) lines arranged perpendicular to a plurality of parallel bit (output) lines. At the intersections of the word lines and bit lines are programmable connection circuits. Each programmable connection includes a memory cell which is programmed to either connect or disconnect one word line to/from one bit line. The word lines receive signals input to the CPLD, and feedback signals from the macrocells. Selected bit lines are connected to the word lines via the programmable connections to route input and feedback signals into selected function blocks. Cross-point interconnect matrices are characterized in that every word line is programmably connectable to every bit line, thereby providing the advantage of 100% routability—that is, every word line can be connected to every bit line within a cross-point interconnect matrix. Another advantage of cross-point interconnect matrices is that two or more signals on the word lines can be logically ANDed together before transmission to the function blocks. Cross-point interconnect matrices are described in U.S. Pat. Nos. 5,028,821 and 5,530,378, which are incorporated herein by reference in their entirety.
Complex programmable logic devices are commonly used in field-programmable systems, i.e., systems whose operational characteristics are designed to be changed or upgraded after they leave the factory. Such systems, also known as embedded systems, utilize the well-known IEEE 1149.1 boundary-scan/JTAG interface to perform in-system testing and programming. Boundary-scan testing and programming is accomplished using a test access port (TAP) on the CPLD device, which is typically a set of four dedicated pins. The boundary-scan/JTAG standard is formally known as IEEE/ANSI standard 1149.1
—
1190, which is well known in the art and therefore not described in detail herein.
Today's complex systems, often consisting of multiple controllers and PLDS, use their controllers to perform in-system programming (ISP) of their CPLDs to adapt to new uses, expand system capability, or correct flaws or shortcomings. In these systems, programmable logic devices are connected in a chain or other topology with a master controller at the top of the chain. Programming includes erasure of existing programmable connections (e.g., logic and input/output paths), programming new connections, or verifying the existing programming. Generically, these programming operations are referred to as “non-mission” operations, in contradistinction to the “mission” operations, the activities for which the system is designed and programmed.
Power loss may occur at any time during mission or non-mission operations. In particular, power loss during programming operations may leave the CPLD in a partially unprogrammed state on power restoration. In such situations, the functional pins of the CPLD may be left in an undefined condition (i.e. either high, low, or floating). If these pins are connected to the address bus of the processor, for instance, the undefined state could preventing the processor from using the address bus to correctly address another device on the bus. Consequently, all system operations in general would be disrupted.
What is needed is an apparatus and a method of operation to ensure that the functional pins of a CPLD will remain in a safe, high impedance, floating (i.e., tri-state logic) condition in the event of power loss during non-mission operations and therefore will affect neither control nor operation of any busses or devices connected to the CPLD.
SUMMARY OF THE INVENTION
An apparatus and a method of operation for programming a programmable logic device (PLD) using a status bit to signal whether an in-system programming (ISP) operation has been completed is described. Systems utilizing a controller or processor often use PLDs to interface to other elements of the system and to the outside environment. Such PLDs are reprogrammed by the system controller using the boun
Bever Hoffman & Harms LLP
Garbowski Leigh Marie
Smith Matthew
Xilinx , Inc.
LandOfFree
Method and apparatus for in-system programming with a status... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for in-system programming with a status..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for in-system programming with a status... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2565207