Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-03-23
2001-11-20
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230030
Reexamination Certificate
active
06320803
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an improved system for testing and for improving the performance of very large integrated scale integrated circuits (VLSI) such as synchronous dynamic random access memory (SDRAM) devices, and to the devices themselves.
BACKGROUND OF THE INVENTION
The density of dynamic random access memory (DRAM) devices has increased dramatically in recent years. Today 64 megabit (MB) devices, each on a single chip with an area of several tens of square millimeters, are commonplace and 256 MB devices with areas under a hundred square millimeters are becoming available. Operating speeds have increased from 50 MHz to over 500 MHz.
In earlier DRAM systems data transfer to or from a memory controller was asynchronous to the system clock to which the controller operations are referenced. But a problem arises with higher speed systems in that all timing parameters for the DRAM must be met for a particular speed sort. In other words, missing or failing to meet any timing parameter can down-sort a very fast part of the system into a slower access bin. This problem gave rise to the development of a synchronous DRAM (SDRAM) which is designed to have an input address and command interface more similar to that of the memory controller. The SDRAMs are that class of memory units which use the system clock to synchronize the interface between the memory controller and the DRAM arrays. Based on operating frequency and number of bits transferred per clock cycle, SDRAMs can provide substantial bandwidth increase over previous DRAMs.
The rapid increase in process and functional complexity in today's synchronous dynamic random access memory (SDRAM) products and VLSLs in general, creates a need for high resolution test methodologies. This requirement is driven by the need to reveal and to characterize subtle process and design interactions that may occur in the product during the technology and design development phase of the product effort. Also, once the product is qualified and in manufacturing production, precision test methodologies are required for code signal development, process learning, and also for yield and product improvement. The invention described hereinafter will illustrate the techniques utilized to implement a “Test Mode” architecture on a 256 MB SDRAM, by way of example. The invention however is applicable to VLSI products in general, as well as other products, and is not restricted solely to SDRAMs.
It is industry practice to subject products, such as SDRAMs, to a period of testing and “burn-in” before they are shipped from the factory. During burn-in the products are operated at substantially higher than normal voltages and temperatures in order to artificially stress them and thereby weed out of a given population of devices those which possibly would fail prematurely in actual operation. A burn-in period may, for example in the case of 256 MB SDRAMs, take as long as sixteen hours. Various test signals applied to the individual devices during a burn-in period are used in an attempt to find inadequate or improper operation of a given device, such as caused by microscopic defects or variations in the physical and/or electrical conditions within that device. It is desirable to be able to shorten by a substantial amount the time required for burn-in, and also to have more effective test signals and a better way of applying them to each device (e.g., an SDRAM) in order to reveal undesirable performance interactions or deficiencies within the device among its various memory arrays or sections. The present invention provides improved test methodologies for VLSIs in general, and SDRAMs in particular, as well as improved products resulting therefrom.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention there is provided a synchronous random access memory (SDRAM) device having in conventional fashion internal memory arrays or banks and having specially added logic circuits (LOGIC CKTs) provided by the invention. By means of these logic circuits, which are controlled by respective “test mode select” (TMSEL) signals, the arrays may be selectively actuated by “test mode control” (TMCNTL) signals applied to the arrays simultaneously. As a result, the respective memory banks of the SDRAM can be operated selectively and/or simultaneously in accordance with a sequence of the TMCNTL signals which are designed to reveal subtle interactions between or among the arrays or banks, such as induced noise, voltage interactions, variable signal delays, and other undesirable conditions which may not be otherwise evident in conventional testing. Knowledge of such interactions is useful in modifying the design or layout of an SDRAM during development in order to minimize or eliminate the interactions and provide a better product. Moreover, because the arrays of the SDRAM can now be tested independently and/or simultaneously, a period of burn-in can be considerably shortened relative to prior-art arrangements.
In a first apparatus aspect, the present invention is directed to apparatus for testing devices. The apparatus comprises a device having a plurality of arrays or banks, circuit means coupled to the arrays for selectively activating the arrays with respective test mode signals, test means, and input-output means. The test means applies through the circuit means a sequence of test mode signals respectively to each array separately and to all of them simultaneously to reveal whether there are defects or undesirable interactions between or amongst arrays. The input-output means sends data to and from the device.
From a second apparatus aspect, the present invention is directed to apparatus for testing devices. The apparatus comprises a device having a plurality of arrays or banks, means for applying to the device address and command signals, circuit means coupled to the arrays for selectively activating the arrays with respective test mode signals, test means, and input-output means. The test means applies through the circuit means a sequence of test mode signals respectively to each array separately and to all of them simultaneously to reveal whether there are defects or undesirable interactions between or amongst arrays. The input-output means sends data to and from the device.
From a third apparatus aspect, the present invention is directed to a very large scale integrated (VLSI) device having a plurality of memory arrays. The device has a plurality of spaced-apart arrays on a semiconductor chip, command and control means for applying command and control signals to the arrays of the device, circuit means coupled to the arrays for selectively activating the arrays with respective test mode signals, test means, and input-output means. The test means applies through the circuit means a sequence of test mode signals respectively to a selected array or arrays to reveal whether there are defects or undesirable interactions between or amongst arrays. The input-output means sends data to and from the arrays.
From a fourth apparatus aspect, the present invention is directed to a synchronous dynamic random access memory (SDRAM) device. The device comprises memory arrays placed respectively at quadrants of a semiconductor chip, means to apply command and control signals to the device, command and control signals to the device, clock means for applying clock signals to the device to synchronize its operation with external equipment, and logic circuit means. The logic circuit means is coupled to the arrays for selectively activating them in desired test mode sequences with respective test mode control (TMCNTL) signals. The device also comprises means for applying TMCNTL signals to the logic circuit means and test means that applies to the logic circuit means test mode select (TMSEL) signals such that any combination of the arrays can be activated into any desired test mode sequences by the test mode control (TMCNTL) signals and the TMSEL signals to reveal whether there are defects in the device or undesirable interactions between arrays. The device also c
Ellis Wayne
Gall Martin
Miyamoto Shinji
Yoshihara Masahiro
Braden Stanton C.
Hoang Huan
Infineon Technologies AC
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