Method and apparatus for improving read/write stability of a sin

Details Method and apparatus for improving read/write stability of a sin Method and apparatus for improving read/write stability of a sin

1998-05-06

1999-11-16

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 36523005, G11C 1100

Patent

active

059869232

ABSTRACT:
A single-ended SRAM cell design reduces SRAM size and provides high storage cell noise margin. A virtual ground line is coupled to the source of the driver NFET of each I/O port inverter of each storage cell in a common bitline column. An isolation mechanism couples the virtual ground line to a low reference voltage during reads and during a write of a "0" to a storage cell, and isolates the virtual ground line from the low reference voltage during a write of a "1" to a storage cell. A clamping device is coupled to the virtual ground line to prevent the potential on the virtual ground line from exceeding the threshold voltage of the isolation mechanism and flipping the stored value in any of the other commonly coupled storage cells when a "1" is being written to another of the commonly coupled storage cells.

REFERENCES:
patent: 4764897 (1988-08-01), Kameyama et al.
patent: 5764564 (1998-04-01), Frake et al.
patent: 5808933 (1998-09-01), Ross, Jr. et al.
patent: 5831896 (1998-11-01), Lattimore et al.

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