Static information storage and retrieval – Read/write circuit – Signals
Patent
1999-02-01
2000-06-20
Hoang, Huan
Static information storage and retrieval
Read/write circuit
Signals
36523003, 36523006, G11C 700
Patent
active
060785322
ABSTRACT:
A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.
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DeJager Gregory L.
Emery Scott A.
Erickson Bradley
Findlater Stewart
Rivers James P.
Cisco Technology Inc.
Hoang Huan
Ross P.C. Sheridan
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