Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-01-09
2010-10-05
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S710000, C365S201000
Reexamination Certificate
active
07809998
ABSTRACT:
A memory circuit includes a memory interface. A first memory receives a first read address from the memory interface. A second memory stores addresses of defective memory locations found in the first memory, receives the first read address from the memory interface, compares the first read address to the addresses stored in the second memory, and, if a matching address is found, reads first data from the second memory. The first memory reads second data from a memory location in the first memory corresponding to the first read address. A multiplexer receives the second data and the first data from the first memory and the second memory, respectively, when the matching address is found, and selectively outputs one of the second data and the first data to the memory interface.
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Azimi Saeed
Sutardja Sehat
Britt Cynthia
Marvell International Ltd.
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