Method and apparatus for improving integrated circuit device...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S199000, C438S275000, C257SE21632

Reexamination Certificate

active

07666720

ABSTRACT:
A method of forming a current mirror device for an integrated circuit includes configuring a reference current source; forming a first field effect transistor (FET) in series with the reference current source, the first FET of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation; and forming a second FET of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation, with a gate terminal of the first FET coupled to a gate terminal of the second FET, and the gate terminals of the first and second FETs coupled to the reference current source; wherein the carrier mobility of the first FET formed on the first portion of the substrate is different than the carrier mobility of the second FET formed on the second portion of the substrate.

REFERENCES:
patent: 4823092 (1989-04-01), Pennock
patent: 5384473 (1995-01-01), Yoshikawa et al.
patent: 5714906 (1998-02-01), Motamed et al.
patent: 6275079 (2001-08-01), Park
patent: 6657223 (2003-12-01), Wang et al.
patent: 6794718 (2004-09-01), Nowak et al.
patent: 6998684 (2006-02-01), Anderson et al.
patent: 7382029 (2008-06-01), Pekarik et al.
patent: 2003/0030056 (2003-02-01), Callaway, Jr.
patent: 2003/0034545 (2003-02-01), Johnson et al.
patent: 2004/0151917 (2004-08-01), Chen et al.
patent: 2004/0195623 (2004-10-01), Ge et al.
patent: 2004/0195646 (2004-10-01), Yeo et al.
patent: 2004/0256700 (2004-12-01), Doris et al.
patent: 2005/0093104 (2005-05-01), Ieong et al.
patent: 2005/0199984 (2005-09-01), Nowak
patent: 2004153256 (2004-04-01), None
M. Shima et al., “<100> Channel Strained-SiGE p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance”, Symposium On VLSI Technology Digest of Technical Papers, 2002, pp. 94-95.
M. Yang et al., “Hign Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations”, IEDM 03, 2003, pp. 453-456.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for improving integrated circuit device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for improving integrated circuit device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving integrated circuit device... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4220439

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.