Abrading – Precision device or process - or with condition responsive... – Condition responsive control for sandblasting
Reexamination Certificate
1998-02-19
2001-02-20
Rose, Robert A. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
Condition responsive control for sandblasting
C451S065000, 43
Reexamination Certificate
active
06190233
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the deposition of dielectric layers during wafer processing, and more specifically to a method and apparatus for performing chemical and physical etchback processes to further improve gap-fill capability.
Interconnections on semiconductor devices are typically made by metal conductors, which in some cases are narrow, closely spaced metal lines. The use of two or more levels of metal conductors requires the deposition of an insulating layer between the layers of metal to avoid a short circuit between conductors or other anomalies.
Thus, one of the primary steps in the fabrication of modern multilevel semiconductor devices is the formation of these insulating layers, which are also referred to as intermetal dielectric layers, or IMD layers. One of the primary methods of forming IMD layers on a semiconductor substrate is by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or “CVD.” Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions produce a desired film. Another CVD method of depositing layers includes plasma-enhanced CVD (PECVD) techniques. Plasma CVD techniques promote excitation and/or dissociation of the reactant gases by the application of energy, such as radio frequency (RF) energy, to excite the reactant gases, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such CVD processes. The relatively low temperature of a PECVD process makes such processes ideal for the formation of insulating layers over deposited metal layers and for the formation of other insulating layers.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing devices with 0.5 &mgr;m and even 0.35 &mgr;m features, and tomorrow's plants soon will be producing devices with even smaller geometries.
As device sizes become smaller and integration density increases, issues that were not previously considered important by the industry are becoming of paramount concern. For example, as circuit densities increase, the spacing between adjacent metal conductors decreases, which causes an increase in the ratio of the height of adjacent conductors to their separation, commonly referred to as the aspect ratio. An increase in the aspect ratio is accompanied by an increase in the likelihood that a deposited insulating layer will not conform to and completely fill the gap between conductors. Thus, as an insulating layer is deposited, an undesirable void may form within the layer between adjacent conductors. Typically, voids are formed when the dielectric deposits on the upper portion of adjacent metal vertical side walls contact each other before the bottom of the gap is filled.
One solution to this problem is to deposit fluorine-doped silicon oxide films, which are also referred to as fluorosilicate glass (FSG) films. Because fluorine is an etching species, it is believed that fluorine doping introduces an etching effect on the growing film. This simultaneous deposition/etching effect slows the deposition on the top of the sidewalls thereby allowing that the bottom of the gap to fill before the top closes.
Another solution to the gap-fill problem is to perform a three-step deposition/etchback/deposition process. In this three-step process, an insulating layer is first partially deposited over a metal layer. Next, a physical etchback step is performed in which the deposited insulation layer is bombarded with argon or a similar gas in a sputtering step. The argon sputtering etches away some of the excess deposits that might otherwise contribute to void formation. After completion of the physical etchback, deposition is completed in the third step.
The three-step deposition/etchback/deposition process provides improved gap-fill capabilities that are suitable for many applications. However, as devices become even smaller, better gap-fill capabilities are desirable for some applications. Hence, there is a need for a method and an apparatus that further improve the gap-fill capability of present dielectric films.
SUMMARY OF THE INVENTION
The present invention provides an insulating layer with improved gap-fill capabilities. Improved gap-fill is obtained by using both chemical and physical etchback steps after deposition of a first portion of the insulating layer. The present invention also includes a method and apparatus for fabricating such a layer.
According to the method of the present invention, a first layer of dielectric material is deposited over a substrate in a processing chamber. The layer is then etched back using a two-step etch process that includes both chemical and physical etchback steps. After the two-step etchback process in completed, a second layer of dielectric material is deposited over the substrate to complete the gap-fill process.
In one embodiment, the two-step etchback process includes a first, chemical etchback step followed by a physical etchback step. In another embodiment of the method of the present invention, the first dielectric layer is etched back using a physical etchback, followed by a chemical etchback. In still yet another embodiment, the first dielectric layer is etched back using more than two alternating chemical and physical etchback steps.
In another preferred embodiment, the first and second dielectric layers are FSG layers, and in a most preferred embodiment these layers are deposited from a process gas that includes silicon provided by tetraethylorthosilicate (TEOS) and fluorine provided by triethoxyfluorosilane (TEFS). Carbon tetrafluoride (CF
4
) is employed as an etchant gas during the chemical etchback step and argon is employed as a sputtering element during the physical etchback step.
These and other embodiments of the present invention, along with many of its advantages and features, are described in more detail in the text below and the attached figures.
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Conners Andrew
Hong Soonil
Lam Anthony
Nault Michael P.
Rana Virendra V. S.
Applied Materials Inc.
Rose Robert A.
Townsend & Townsend & Crew
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