Method and apparatus for improving bus master performance

Details Method and apparatus for improving bus master performance Method and apparatus for improving bus master performance

2007-06-12

2007-06-12

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S310000, C713S320000, C713S321000, C713S322000, C713S324000, C713S330000, C713S340000

Reexamination Certificate

active

11189688

ABSTRACT:
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

REFERENCES:
patent: 6125450 (2000-09-01), Kardach
patent: 6446215 (2002-09-01), Meyer et al.
patent: 6560712 (2003-05-01), Arends et al.
patent: 6971033 (2005-11-01), Ma
patent: 6976132 (2005-12-01), Dieffenderfer et al.
patent: 6981081 (2005-12-01), Stevens et al.
patent: 7028200 (2006-04-01), Ma

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