Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2005-11-29
2005-11-29
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
C710S110000, C710S113000, C710S116000, C710S117000, C710S119000, C710S123000, C710S124000, C710S309000, C345S531000, C345S535000, C345S541000
Reexamination Certificate
active
06971033
ABSTRACT:
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.
REFERENCES:
patent: 5699540 (1997-12-01), Vanka et al.
patent: 5819087 (1998-10-01), Le et al.
patent: 5822758 (1998-10-01), Loper et al.
patent: 6154838 (2000-11-01), Le et al.
patent: 6184906 (2001-02-01), Wang et al.
patent: 6333745 (2001-12-01), Shimomura et al.
patent: 6654833 (2003-11-01), LaBerge
patent: 6704846 (2004-03-01), Wu et al.
patent: 6750782 (2004-06-01), Byun
patent: 6857035 (2005-02-01), Pritchard et al.
patent: 6910088 (2005-06-01), LaBerge
patent: 2002/0194509 (2002-12-01), Plante et al.
patent: 2003/0237012 (2003-12-01), Jahagirdar et al.
Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, Phoenix Technologies Ltd., Toshiba Corporation,Advanced Configuration and Power Interface Specification, Revision 1.0b(Feb. 2, 1999).
Jedec Standard Double Data Rate (DDR) SDRAM Specfication,JESD79, Jedec Solid State Technology Association, Release 1(Jun. 2000).
PCI Special Interest Group,PCI Local Bus, Small PCI Specification, Verison 1.5a, Final (Dec. 23, 1996).
Broadcom Corporation
Elamin A.
McAndrews Held & Malloy, Ltd
LandOfFree
Method and apparatus for improving bus master performance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for improving bus master performance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving bus master performance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3517300