Method and apparatus for improved reliability and reduced...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C713S300000, C713S310000, C713S320000, C713S321000, C713S323000, C713S324000, C713S330000, C713S340000

Reexamination Certificate

active

10459011

ABSTRACT:
A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.

REFERENCES:
patent: 6118306 (2000-09-01), Orton et al.
patent: 6125450 (2000-09-01), Kardach
patent: 6415388 (2002-07-01), Browning et al.
patent: 6678831 (2004-01-01), Mustafa et al.
patent: 6704877 (2004-03-01), Cline et al.
patent: 6735105 (2004-05-01), Nakano
patent: 6754837 (2004-06-01), Helms
patent: 6785829 (2004-08-01), George et al.
patent: 6792551 (2004-09-01), Dai
patent: 6864600 (2005-03-01), Malinovitch
patent: 6922783 (2005-07-01), Knee et al.
patent: 6941480 (2005-09-01), Dai
patent: 6985952 (2006-01-01), Bohrer et al.
patent: 6988211 (2006-01-01), Cline et al.
patent: 6993669 (2006-01-01), Sherburne, Jr.
patent: 7000133 (2006-02-01), Dodd et al.
patent: 2003/0075735 (2003-04-01), Nakano
patent: 2003/0237012 (2003-12-01), Jahagirdar et al.
patent: 2004/0117677 (2004-06-01), Jahagirdar et al.
patent: 2004/0163005 (2004-08-01), Kardach et al.
patent: 2005/0091548 (2005-04-01), George et al.
patent: 2005/0149929 (2005-07-01), Srinivasan et al.
“Method for Reducing Power in the Halt and Stop Grant CPU states,” published anonymously at www.ip.com on Sep. 25, 2002 with identifier #IPCOM000009890D.
U.S. Appl. No. 11/323,254, entitled Method and Apparatus for a Zero Voltage Processor Sleep State, filed Dec. 30, 2005, by Sanjeev Jahagirdar et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for improved reliability and reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for improved reliability and reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improved reliability and reduced... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3880144

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.