Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1997-09-26
1999-10-19
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
710 57, 713323, 369 54, 369 60, 711154, G06F 1300
Patent
active
059681470
ABSTRACT:
Disclosed is a system for minimizing the utilization of an I/O bus by a first data-writing peripheral device that is connected to the I/O bus. The system has a second peripheral device that shares the I/O bus connection. The system includes the operations of transferring data to a drive buffer that is in the first data-writing peripheral device. The transferring being configured to continue until the drive buffer has reached a full state. Performing a pre-write calibration of the first data-writing peripheral device after the drive buffer has reached the full state. Commencing a writing of a portion of the data contained in the drive buffer, such that the first data received by the drive buffer is written first. The system further including releasing the I/O bus connection by placing a write thread of the first data-writing peripheral device in a sleep mode. Wherein when the write thread of the first data-writing peripheral device is in the sleep mode the I/O bus connection is made available to the second peripheral device while the first data-writing peripheral device is not transferring data. The system further includes continually bring the write thread of the first data-writing peripheral device out of the sleep mode to perform a data burst when the drive buffer has emptied to a critical level and then placing the write thread back to the sleep mode after the data burst.
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Berhan Michael D.
D'Amato Andrea
Diemer Peter C.
McMurdie Michael S.
Polfer Daniel A.
Adaptec, Inc.
Auve Glenn A.
Dharia Rupal
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