Method and apparatus for improved memory core testing

Details Method and apparatus for improved memory core testing Method and apparatus for improved memory core testing

2005-03-08

2005-03-08

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S030000, C365S201000

Reexamination Certificate

active

06865701

ABSTRACT:
A memory unit is described that has a controller coupled to a memory core through an interface circuit. The interface circuit has a test data input that receives test data from the controller. The interface circuit also has a system data input that receives data from a system. The interface circuit has a data output that is coupled to a data input of the memory core.

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