Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2000-02-02
2003-09-09
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S211000
Reexamination Certificate
active
06618801
ABSTRACT:
FIELD
The present invention relates to digital computer systems, and more particularly but not by way of limitation, to methods and an apparatus for implementing two or more architectures on a chip.
BACKGROUND
Microprocessors exist that implement a reduced instruction set computing (RISC) instruction set architecture (ISA) and an independent complex instruction set computing (CISC) ISA by emulating the CISC instruction with instructions native to the RISC instruction set. Instructions from the CISC ISA are called “macroinstructions.” Instructions from the RISC ISA are called “microinstructions.”
Existing microprocessors do not implement these two architectures as efficiently as can be done. Some existing processors use more global wires routing data to many parts of the chip. This makes chip routing more difficult and less efficient. These techniques also complicate the timing and the pipeline of the processor. It is desirable to create an efficient means of implementing both architectures on a single chip, while leveraging existing hardware. In particular, it is desirable to localize processing and dispatching of the instructions, with minimal impact on the existing execution engine.
SUMMARY
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexor or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.
The present invention is also a computer system having a processor capable of implementing two architectures. The computer system has a fetch engine to retrieve instructions, an execution engine to execute the instructions, and an emulation engine to decode macroinstructions into microinstructions before their execution. The emulation engine uses a bundler to bundle microinstructions and other information into groups. These bundles are delivered to the execution engine in parallel.
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Wolfe, A., “Patents shed light on Merced's Innards”, Electronic Engineering Times, Feb. 15, 1999.
Brockmann Russell C
Knebel Patrick
Lamb Joel D
Safford Kevin David
Soltis Jr. Donald Charles
Chan Eddie
Harkness Charles
Hewlett--Packard Development Company, L.P.
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