Method and apparatus for implementing .times.2 parity DRAM for 1

Details Method and apparatus for implementing .times.2 parity DRAM for 1 Method and apparatus for implementing .times.2 parity DRAM for 1

1991-05-31

1994-02-15

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Testing

3652257, G11C 700

Patent

active

052873110

ABSTRACT:
A 1M.times.2 parity DRAM is salvaged from a defective 1M.times.4 parity DRAM having two or less unrepairable memory quadrants. Circuits are designed so "any" combination of 2 good quadrants can be accessed as a result of fuse blowing and steering logic which is controlled by the fuse signals.

REFERENCES:
patent: 4703436 (1987-10-01), Varshney
patent: 5109360 (1992-04-01), Inazumi et al.
patent: 5126973 (1992-06-01), Gallia et al.

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