Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-20
2007-03-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10618416
ABSTRACT:
A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
REFERENCES:
patent: 5197016 (1993-03-01), Sugimoto et al.
patent: 6311316 (2001-10-01), Huggins et al.
patent: 6643833 (2003-11-01), Nishioka et al.
patent: 6757878 (2004-06-01), Srinivasan et al.
patent: 6763506 (2004-07-01), Betz et al.
patent: 6779169 (2004-08-01), Singh et al.
patent: 6817005 (2004-11-01), Mason et al.
patent: 6871328 (2005-03-01), Fung et al.
patent: 2002/0089348 (2002-07-01), Langhammer
Betz Vaughn
Borer Terry P.
Brown Stephen D.
Pantofaru Caroline
Quan Gabriel
Cho L.
Siek Vuthe
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