Method and apparatus for implementing redundant memory...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07882479

ABSTRACT:
A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.

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patent: 6243829 (2001-06-01), Chan
patent: 6802023 (2004-10-01), Oldfield et al.
patent: 6854043 (2005-02-01), Hargis et al.
patent: 6978397 (2005-12-01), Chan
patent: 2001/0016920 (2001-08-01), Chan
patent: 2002/0133740 (2002-09-01), Oldfield et al.
patent: 2002/0133743 (2002-09-01), Oldfield et al.

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